87dd96bbbe
anv: drop support for VK_NV_mesh_shader
...
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071 >
2023-07-14 08:27:14 +00:00
ed72d6e2a7
hasvk: remove dead code & comments related to mesh shading
...
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071 >
2023-07-14 08:27:14 +00:00
67a8b70c57
anv: hide exec_flags selection inside the i915 backend
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Hyunjun Ko <zzoon@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24073 >
2023-07-13 17:12:26 +00:00
39f547381c
isl: Set MOCS to uncached for MTL stream-out
...
Without this change various OpenGL CTS tranform feedback tests were
failing.
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823 >
2023-07-13 00:32:13 -07:00
fa47c82fbe
isl/dev: Add uncached MOCS value
...
Rework:
* Jordan: Add uncached for all platforms (Requested by Francisco)
* Jordan: Use gen7 & gen8 values suggested by Francisco
* Jordan: Fix IVB and CHV MOCS mistakes pointed out by Francisco
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823 >
2023-07-13 00:32:13 -07:00
ef105f8cce
genxml/chv: Add MEMORY_OBJECT_CONTROL_STATE_CHV to document compared to BDW
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823 >
2023-07-13 00:32:09 -07:00
90535d7aef
genxml/hsw: Add additional MOCS field enumerations
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823 >
2023-07-13 00:32:05 -07:00
492b07625d
anv,iris,hasvk: Use ISL_SURF_USAGE_STREAM_OUT_BIT for setting stream-out MOCS
...
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823 >
2023-07-12 23:47:25 -07:00
6b5082f5d5
isl: Add ISL_SURF_USAGE_STREAM_OUT_BIT
...
Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823 >
2023-07-12 23:47:03 -07:00
a762fa27db
anv: limit stack usage for anv_surface_state
...
Each one is 136 bytes.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24109 >
2023-07-12 12:00:10 +00:00
deaf4f2d57
anv: pass anv_surface_state using a pointer
...
It's 136 bytes, so passing it by stack is wasteful.
CID: 1531860
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24109 >
2023-07-12 12:00:09 +00:00
fb070b1dfd
anv: fix how NULL buffer_view is handled in anv_descriptor_set_write_buffer_view
...
CID: 1531855
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24109 >
2023-07-12 12:00:09 +00:00
9383009809
nir: rename has_txs to has_texture_scaling
...
Convert it to an opt-in for backends to prefer and use nir_load_texture_scale
instead of txs for nir lowerings.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com >
Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054 >
2023-07-12 10:03:06 +00:00
0c778ec3c8
anv: Adds a workaround for HEVC decoding on some old platforms.
...
HEVC support on Gfx9 is only available on VCS0. So limit the number of video queues
to the first VCS engine instance.
We should be able to query HEVC support from the kernel using the engine query uAPI,
but this appears to be broken : https://gitlab.freedesktop.org/drm/intel/-/issues/8832
When this bug is fixed we should be able to check HEVC support to determine the
correct number of queues.
Closes : mesa/mesa#9172 , mesa/mesa#9314
Signed-off-by: Hyunjun Ko <zzoon@igalia.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24065 >
2023-07-12 15:34:28 +09:00
73e191924c
nir: Add a reg_intrinsics flag to nir_convert_from_ssa
...
It doesn't do anything yet. We leave that to the subsequent patches so we can
keep the tree-wide refactor as simple as possible.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089 >
2023-07-12 01:34:27 +00:00
a85b84ba1e
anv: fix utrace signaling with Xe
...
utrace submits can either have a batch or not.
When there is a batch, the utrace vk_sync is signaled by the utrace
batch (because utrace does a timestamp buffer copy using its own
batch). When there is no batch, the utrace vk_sync should be signaled
by the application batch (no timestamp copy required, utrace can read
the timestamps when the application batch has completed).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: fdea48df5ejose.souza@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24085 >
2023-07-11 16:27:06 +00:00
bd27faf083
treewide: remove unused nir_builder
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038 >
2023-07-10 19:20:17 +00:00
48a25ef700
treewide: Remove all usage of nir_builder_init with nir_builder_create and nir_builder_at
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038 >
2023-07-10 19:20:17 +00:00
66a6f48747
anv: Drop depth cache flush requirement after depth clear/resolve
...
From Bspec 46959, a programming note applicable to Gfx12+:
"Since HZ_OP has to be sent twice (first time set the clear/resolve
state and 2nd time to clear the state), and HW internally flushes the
depth cache on HZ_OP, there is no need to explicitly send a Depth
Cache flush after Clear or Resolve."
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027 >
2023-07-10 18:03:39 +00:00
b0bbd9c0d3
nir: do not needlessly rely on optimizations
...
We're going to do this rewrite once we get to nir_opt_algebraic anyway,
so let's save a little bit of needless work here.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24004 >
2023-07-10 16:06:40 +02:00
8166c1f8c1
intel/genxml: Drop incorrect compute aux-inv register entry
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
cc6c35518f
intel/genxml: Fix typo in CCS cache flush enable
...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
c328638b3b
anv: Use correct CCS0 aux-map register offset in pipe flush
...
According to Bspec, COMPCS0_CCS_AUX_INV register offset
is 042C8h and COMPCS0_AUX_TABLE_BASE_ADDR is defined to 042C0h.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
1fb9460913
anv: Program compute aux-map base address during queue init
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
b4ab4e8549
intel/genxml: Add COMPCS0 aux-table registers
...
Bspec 43904 defines COMPCS0_CCS_AUX_INV to 042C8h and Bspec 43882
defines COMPCS0_AUX_TABLE_BASE_ADDR to 042C4h.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958 >
2023-07-07 18:05:47 +00:00
7471bc2574
intel/vulkan: Convert to use nir_foreach_function_impl when possible
...
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24040 >
2023-07-07 14:02:40 +00:00
1e655b2f25
clc: rework optional subgroup feature
...
OpenCL 3.0 core requires __opencl_c_subgroups to be set, the OpenCL
cl_khr_subgroups extenions can only be enabled if and only if the driver
guarentees independent forward progress between subgroups.
See CL_DEVICE_SUB_GROUP_INDEPENDENT_FORWARD_PROGRESS for more information.
Signed-off-by: Karol Herbst <git@karolherbst.de >
Reviewed-by: Nora Allen <blackcatgames@protonmail.com >
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22893 >
2023-07-07 12:27:35 +00:00
2e3c445b68
ci/anv: Add testing of the GLES CTS using ANGLE on TGL.
...
We're interested in a Vulkan-only stack in Chrome OS, where Android's GLES
would be provided by ANGLE-over-Venus-over-ANV. Let's get some testing
covering ANGLE-on-ANV first.
This is structured as a single partial job pre-merge to catch most
regressions, and a longer manual job to do full coverage for when you need
to update the xfails list.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20163 >
2023-07-06 23:12:30 +00:00
703102d7cb
intel/ci: fix skips definitions
...
Skips are regexes, not globs :)
Signed-off-by: Eric Engestrom <eric@igalia.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24024 >
2023-07-06 17:18:15 +00:00
c26c0a36d3
intel/fs: disable coarse pixel shader with interpolater messages at sample
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9292
Reviewed-by: Emma Anholt <emma@anholt.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23962 >
2023-07-06 12:48:52 +00:00
d0e6809ee5
anv/video: fix to support HEVC 10bit on some of 9th gens.
...
From Broxton and Kabylake, it started supporting HEVC 10-bit decoding.
Fixes: 649e12c897zzoon@igalia.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23985 >
2023-07-05 00:20:18 +00:00
59aa49494c
anv: Drop unnecessary intel_canonical_address() calls around bo->offset
...
bo->offset is set as canonical address no need to do it over again.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23977 >
2023-07-04 15:24:04 +00:00
27e20c8726
anv: Drop unnecessary intel_canonical_address() call around anv_address_physical()
...
anv_address_physical() already returns a canonical address.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23977 >
2023-07-04 15:24:04 +00:00
2fa4fe2c85
anv: Fix some mismatches of canonical and regular addresses around anv_bo_vma_alloc_or_close()
...
anv_vma_alloc() returns a canonical address, but explicit_address is a
regular address. This mismatch can potentially cause issues.
So here making bo->offset as always canonical address by converting it
in the explicit case and fixing the only caller that was caling
anv_bo_vma_alloc_or_close() with a canonical address.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23977 >
2023-07-04 15:24:04 +00:00
7ed9ec70c0
intel/compiler: simplify reading of gl_NumWorkGroups in task/mesh
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22334 >
2023-07-04 09:15:08 +00:00
1ac1d5d62e
anv,intel/compiler: enable shortcut in wg id to wg idx lowering on >= gfx12.5
...
This speeds up vk_meshlet_cadscene in "VK mesh ext" renderer by 1.4%
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22334 >
2023-07-04 09:15:08 +00:00
7ec1ef75d3
intel/compiler: pass num_workgroups from task to mesh shaders
...
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22334 >
2023-07-04 09:15:08 +00:00
fd4d0e1cc2
st/mesa: Set gl_config.floatMode based on color_format
...
Sets the float color component type in st_visual_to_context_mode()
ensuring float color values are not clamped.
Fixes dEQP-EGL.functional.wide_color.window_fp16_default_colorspace on
asahi, iris and most likely every other driver having it marked as fail
or flake.
Closes : mesa/mesa#9276
Signed-off-by: Janne Grunau <j@jannau.net >
Reviewed-by: Adam Jackson <ajax@redhat.com >
Acked-by: David Heidelberg <david.heidelberg@collabora.com >
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23914 >
2023-07-04 00:23:40 +00:00
649e12c897
anv_video: reject decoding of unsupported profiles and formats
...
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Dave Airlie <airlied@redhat.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23954 >
2023-07-03 23:48:48 +00:00
c142736f52
anv: Fix compute maximum number of threads value
...
There is no mention in spec about subtract one of the number of
threads, also Iris and blorp code don't subtract.
Alchemist PRMs: Volume 2a: Command Reference: Instructions: CFE_STATE: Maximum Number of Threads:
Normally set to the maximum number of threads: (# EUs) * (# threads/EU)
Cc: mesa-stable
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23973 >
2023-07-03 22:53:49 +00:00
05269047d3
intel: Use nir_builder_at
...
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23883 >
2023-07-03 15:21:38 +00:00
feea00a6c4
anv: retry batchbuffer submission with i915
...
Reviewed-by: José Roberto de Souza <jose.souza@intel.com >
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23950 >
2023-06-30 19:51:33 +00:00
c3110ef1e9
intel/compiler: reuse previously computed bitsize
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23933 >
2023-06-30 09:19:57 +00:00
7f48c70bab
intel/compiler: construct masks instead of using magic values
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23933 >
2023-06-30 09:19:57 +00:00
eeb6515096
intel/isl: tile 64 calculations work with 1D surfaces
...
Depth/stencil surfaces cannot be linear but they can be 1D, so they
end up being tile64 when sparse (as we force every sparse resource to
be either tile64 or linear).
According to the "1D surfaces" page from BSpec, our driver treats 1D
surfaces as 2D surfaces with a height of 1 texel, since we don't
enable the corresponding bit from HAS_SLICE_CHICKEN7. And since we
support 2D surfaces, we should also support 1D.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com >
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22974 >
2023-06-29 23:30:05 +00:00
bafbfc57ea
anv: flush data cache before emitting availability
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23814 >
2023-06-29 22:11:35 +00:00
6535b0c0ea
intel/genxml: Update RENDER_SURFACE_STATE Fields
...
I went through the RENDER_SURFACE_STATE docs today and found a number
of fields that are simply gone, marked as "must be zero", or had their
enum meanings change. Update those here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684 >
2023-06-29 21:45:14 +00:00
4affaced9d
intel/genxml: Fix gen_sort_tags.py to handle mbz/mbo
...
mbz and mbo are base types and not a structure to find as a dependency.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684 >
2023-06-29 21:45:13 +00:00
12f93d06e9
isl: Don't set "Enable Unorm Path in Color Pipe" on Alchemist
...
This bit no longer exists and is marked MBZ. I assume that the
optimization is just permanently enabled; this was always a basically
a chicken bit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684 >
2023-06-29 21:45:13 +00:00
4f3890dd87
anv: move WA 1607854226 to use the WA infrastructure
...
Signed-off-by: Rohan Garg <rohan.garg@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23929 >
2023-06-29 16:22:59 +00:00
Marcin Ślusarz