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isl/dev: Add uncached MOCS value

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Rework:
 * Jordan: Add uncached for all platforms (Requested by Francisco)
 * Jordan: Use gen7 & gen8 values suggested by Francisco
 * Jordan: Fix IVB and CHV MOCS mistakes pointed out by Francisco

Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>
This commit is contained in:
Jordan Justen
2023-06-22 18:05:41 -07:00
parent ef105f8cce
commit fa47c82fbe
2 changed files with 37 additions and 0 deletions
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src/intel/isl/isl.c
+36
View File
@@ -115,10 +115,14 @@ isl_device_setup_mocs(struct isl_device *dev)
dev->mocs.internal = 1 << 1;
/* Displayables cached to L3+L4:WT */
dev->mocs.external = 14 << 1;
/* Uncached - GO:Mem */
dev->mocs.uncached = 5 << 1;
} else if (intel_device_info_is_dg2(dev->info)) {
/* L3CC=WB; BSpec: 45101 */
dev->mocs.internal = 3 << 1;
dev->mocs.external = 3 << 1;
/* UC - Coherent; GO:Memory */
dev->mocs.uncached = 1 << 1;
/* XY_BLOCK_COPY_BLT MOCS fields have programming notes which say:
*
@@ -150,11 +154,15 @@ isl_device_setup_mocs(struct isl_device *dev)
* and flushed at bottom of each submission.
*/
dev->mocs.external = 5 << 1;
/* UC */
dev->mocs.uncached = 1 << 1;
} else {
/* TC=1/LLC Only, LeCC=1/UC, LRUM=0, L3CC=3/WB */
dev->mocs.external = 61 << 1;
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
dev->mocs.internal = 2 << 1;
/* Uncached */
dev->mocs.uncached = 3 << 1;
/* L1 - HDC:L1 + L3 + LLC */
dev->mocs.l1_hdc_l3_llc = 48 << 1;
@@ -166,6 +174,8 @@ isl_device_setup_mocs(struct isl_device *dev)
dev->mocs.external = 1 << 1;
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
dev->mocs.internal = 2 << 1;
/* Uncached */
dev->mocs.uncached = (dev->info->ver >= 11 ? 3 : 0) << 1;
} else if (dev->info->ver >= 8) {
/* MEMORY_OBJECT_CONTROL_STATE:
* .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
@@ -179,6 +189,20 @@ isl_device_setup_mocs(struct isl_device *dev)
* .AgeforQUADLRU = 0
*/
dev->mocs.internal = 0x78;
if (dev->info->platform == INTEL_PLATFORM_CHV) {
/* MEMORY_OBJECT_CONTROL_STATE:
* .MemoryType = UC,
* .TargetCache = NoCaching,
*/
dev->mocs.uncached = 0;
} else {
/* MEMORY_OBJECT_CONTROL_STATE:
* .MemoryTypeLLCeLLCCacheabilityControl = UCUncacheable,
* .TargetCache = eLLCOnlywheneDRAMispresentelsegetsallocatedinLLC,
* .AgeforQUADLRU = 0
*/
dev->mocs.uncached = 0x20;
}
} else if (dev->info->ver >= 7) {
if (dev->info->platform == INTEL_PLATFORM_HSW) {
/* MEMORY_OBJECT_CONTROL_STATE:
@@ -187,6 +211,11 @@ isl_device_setup_mocs(struct isl_device *dev)
*/
dev->mocs.internal = 1;
dev->mocs.external = 1;
/* MEMORY_OBJECT_CONTROL_STATE:
* .LLCeLLCCacheabilityControlLLCCC = 1,
* .L3CacheabilityControlL3CC = 0,
*/
dev->mocs.uncached = 2;
} else {
/* MEMORY_OBJECT_CONTROL_STATE:
* .GraphicsDataTypeGFDT = 0,
@@ -195,10 +224,17 @@ isl_device_setup_mocs(struct isl_device *dev)
*/
dev->mocs.internal = 1;
dev->mocs.external = 1;
/* MEMORY_OBJECT_CONTROL_STATE:
* .GraphicsDataTypeGFDT = 0,
* .LLCCacheabilityControlLLCCC = 0,
* .L3CacheabilityControlL3CC = 0,
*/
dev->mocs.uncached = 0;
}
} else {
dev->mocs.internal = 0;
dev->mocs.external = 0;
dev->mocs.uncached = 0;
}
}
src/intel/isl/isl.h
+1
View File
@@ -1293,6 +1293,7 @@ struct isl_device {
struct {
uint32_t internal;
uint32_t external;
uint32_t uncached;
uint32_t l1_hdc_l3_llc;
uint32_t blitter_src;
uint32_t blitter_dst;