0d4368b22a
panfrost: Don't force early-z with occlusion query
...
..even if there is no z/s enabled. Fixes
dEQP-GLES31.functional.fbo.no_attachments.* on Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
e4592d5651
panfrost: Simplify Midgard blend disable
...
Probably a bit faster too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
2af0c02ffa
panfrost: Clarify how fs_sidefx works with oq
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
22a973601b
pan/mdg: Stub memory_barrier{_image}
...
Same as we do for Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
21d06a41f7
pan/mdg: Make -Wswitch happy
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
34c6d105f6
pan/mdg: Use consistent casing in midgard_print
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
c88c5b1218
panfrost: Assert alignment of indirect records
...
Continuation records need alignment, this shows they already have it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
4b52b0841f
panfrost: Make instancing code more obvious
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
552fdc7ea4
panfrost: Fix src_offset data type
...
We treat it as signed but had it marked as unsigned. It can be negative
in obscure cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
afc4ebdcc0
panfrost: Align NPOT divisor records
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
1760511e02
panfrost: Add util_draw_indirect() debug path
...
Useful for finding problems with the GPU indirect path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
d61162af50
panfrost: Zero r_dimension for buffer textures
...
Instead of reading wrong side of the union (undefined behaviour). Fixes
a GenXML assertion failure in
KHR-GLES31.core.texture_buffer.texture_buffer_texture_buffer_range
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
a78487f795
panfrost: Fix crc_valid condition
...
Fixes fails in dEQP-GLES31.functional.texture.border_clamp.* when run in
parallel with certain other tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
729b8c55f4
panfrost: Simplify compute_checksum_size formula
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
3525ad7c45
panfrost: Fix vertex image attribute overrun
...
Images take a continuation record, don't scribble zeroes over.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Fixes: dc85f65e05https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
a5ec1e7f75
pan/bi: Force u32 for flat varyings
...
Since the GLSL compilers will pack together flat varyings with no regard
to type, under the assumption the backend can deal with it. I guess we
can deal with it then... Fixes fails in
dEQP-GLES31.functional.separate_shader.random.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
b9127ecbb1
panfrost: Use varying format from frag shader
...
Needed to fix up flat varyings to u32 due to TGSI brokenness. If we wack
TGSI, we can drop this.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
58cbf10cdb
panfrost: Correctly size varyings
...
The same slot could be specified multiple times with different
location_frac out of order, so we use two passes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
16e6657132
pan/indirect_draw: Fix 1 instance, nonzero divisor
...
Instead of doing a complicated hack with the POT divisor, just zero the
stride of the linear attribute buffer like we do on the CPU.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
14da452598
pan/indirect_draw: Use unsigned comparisons
...
Instead of signed -- get the types right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
5ea73dbed9
pan/indirect: Factor out is_power_of_two_or_zero
...
The function is complicated enough as it is -- hide the bit twiddling
behind a helper function.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
c25a40d535
panfrost: Default indirect attributes to 1D type
...
Avoids some complexity in the indirect draw happy path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
0566fa2db4
panfrost: Use util_last_bit for images
...
Probbaly more correct for hols in image_mask.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
619b1bc23b
panfrost: Be explicit in image modifier handling
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
5ed37ebfee
panfrost: Separate image attribute and buffer emit
...
Trying to disentangle attributes and attribute buffers, so here's
a leaf node for that change.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
f14dbc02fb
panfrost: Don't duplicate attribute buffers
...
If the (vbi, divisor) tuple matches, we can save an attribute buffer
descriptor. We do the linking at CSO create time. This should be a bit
more cache friendly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
61b83fba27
panfrost: Disable AFBC on v7
...
Broken in several ways. Hide it until we can get this sorted, and have a
test plan to keep it sorted.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Cc: mesa-stable
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
655983d328
panfrost: Add missing 'Reverse issue order flag'
...
Should fix an issue I'm seeing. Spoiler alert, it does not.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
317dd5b327
panfrost: Remove AFBC format fixups
...
It's too complicated and probably for no actual benefit. The main reason
we have BGR formats is for display, but that's export and doesn't get
hit by this path. Internal BGRA textures are possible with a Mesa
extension but sufficiently rare that I regret suggesting this as a
possible optimization. My apologies, and thanks for the fish.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Acked-by: Boris Brezillon <boris.brezillon@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
e111464bfc
pan/bi: Don't allocate past the end of the reg file
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
47e0cce820
pan/bi: Track words instead of bytes in RA
...
Reduces RA memory footprint by 4x, fixing an OOM in the following dEQP
test that otherwise would allocate 8GB of memory...
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
dbc346d659
pan/bi: Simplify spill code
...
Now allow spilling all nodes. Fixes failed spilling in
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.21
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
6dbaae77d9
pan/bi: Emit a dummy ATEST if needed
...
Match what the blob does, since Bifrost has so many random errata we'd
be fools not to.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
b947ab8b10
pan/bi: Lower 64-bit ints again
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
95458c4033
pan/bi: Lower stores with component != 0
...
If the shader packs multiple varyings into the same location with
different location_frac, we'll need to lower to a single varying store
that collects all of the channels together. This is not trivial during
code gen, but it is trivial to do in NIR right before codegen by relying
on nir_lower_io_to_temporaries. Since we're guaranteed all varyings will
be written exactly once, in the exit block, we can scan the shader
linearly and collect stores together in a single pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
de42707101
pan/bi: Lower loads with component > 0
...
We have no native way to swizzle out a nonzero component in a load, but
we can simply load extra components and do the swizzle in shader
instructions. This is inefficient, since it loads data to discard
immediately, but it's required for conformance in some edge cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
5c0e5d4d2d
pan/bi: Handle images in vertex shaders
...
We need to offset by the number of attributes, since the primary
attribute table is shared for images and vertex attributes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
071165e082
pan/bi: Model +BLEND clobbering of r48
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
4663afd8ab
pan/bi: Don't restrict the register file in non-blend shaders
...
Now that preloading is handled correctly, there's nothing 'special'
about R59 and up, so this gets us a few more registers to work with.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
35c7fefc8f
pan/bi: Allow move/sink in blend shaders
...
Now that we handle precolouring we don't need to workaround anything.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
3d851f3b8e
pan/bi: Model interference with preloaded regs
...
Now that we have affinity masks in RA, we can handle this as an easy
case of register liveness analysis, rather than creating pseudo-nodes
and trying hard to coalesce the resulting moves.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
8d4ce240be
pan/bi: Explicit zero reg_live_{in, out} when needed
...
I want to use these fields for a similar purpose in the register
allocator, so they won't be zero anymore for scheduling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
98f072e21b
pan/bi: Inline spilling in RA
...
Should be faster for both spill and not spill cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
80a58dc2e6
pan/bi: Use explicit affinities in RA
...
Inline LCRA to allow us to make the change without disrupting Midgard,
and get some nice cleanup from doing so.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
9d7e25a9a9
pan/bi: Allow IADD.u32 on FMA as *IADDC
...
There's a common special case, slight boost in scheduler freedom.
total nops in shared programs: 101130 -> 101048 (-0.08%)
nops in affected programs: 1677 -> 1595 (-4.89%)
helped: 13
HURT: 0
helped stats (abs) min: 6 max: 8 x̄: 6.31 x̃: 6
helped stats (rel) min: 3.24% max: 25.00% x̄: 7.42% x̃: 4.48%
95% mean confidence interval for nops value: -6.76 -5.85
95% mean confidence interval for nops %-change: -12.02% -2.81%
Nops are helped.
total clauses in shared programs: 27076 -> 27075 (<.01%)
clauses in affected programs: 8 -> 7 (-12.50%)
helped: 1
HURT: 0
total quadwords in shared programs: 113142 -> 113113 (-0.03%)
quadwords in affected programs: 1935 -> 1906 (-1.50%)
helped: 13
HURT: 0
helped stats (abs) min: 2 max: 4 x̄: 2.23 x̃: 2
helped stats (rel) min: 0.95% max: 7.50% x̄: 2.16% x̃: 1.26%
95% mean confidence interval for quadwords value: -2.59 -1.87
95% mean confidence interval for quadwords %-change: -3.45% -0.88%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
7aefd6c1ba
pan/bi: Track liveness while scheduling
...
If we know that a value is killed in the next tuple, there is no need to
write it out to the register file. We already handled this as a packing
fixup. However, avoiding this write also frees up an extra slot in the
register block, which offers additional scheduling freedom. To take
advantage of this, we extend liveness analysis to work while scheduling,
and modify the schedulable predicate accordingly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
20809daa9a
pan/bi: Add post-RA optimizer
...
Delete coalesced moves. Now this is trivial! See e.g shaders/tesseract/118.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
4ed000cf3f
pan/bi: Bundle after RA
...
Flag day change to swap the order of the "scheduler" with the register
allocator. This gives RA much more freedom without significantly
hndering bundling.
It also opens up the door to Adult-level Scheduling which would occur
prior to bundling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
afa4a1d496
pan/bi: Fix bi_rewrite_passthrough ordering
...
The ordering is irrelevant for SSA form input, but is very relevant for
register input.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:10 +00:00
246beb15cf
pan/bi: Simplify TEXC codegen for sr_count=0
...
Obscure case.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123 >
2021-06-10 18:06:09 +00:00
Alyssa Rosenzweig