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Author SHA1 Message Date
Caio Oliveira
f48b3bee31 intel/brw: Split off assembler logic into library 
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30006>
 2024-07-12 19:34:23 +00:00
Faith Ekstrand
1f906f8715 zink/kopper: Set VK_COMPOSITE_ALPHA_OPAQUE_BIT when PresentOpaque is set 
This is required for EGL_EXT_present_opaque to work correctly.

Fixes: 8ade5588e3 ("zink: add kopper api")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11007
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30133>
 2024-07-12 15:22:44 +00:00
Mike Blumenkrantz
70b40fd2a0 zink: modify some buffer mapping behavior for buffer replacement srcs 
if the src for a replace_buffer call is mapped after replacement:
* avoid clearing access flags
* update valid range

the pointer access here is always safe because the only case in which
this scenario can occur is if tc is forced to sync immediately after
creating a replaceent buffer, and the replacement buffer's lifetime
will always be exceeded by the lifetime of the real buffer

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30107>
 2024-07-12 12:29:47 +00:00
Mike Blumenkrantz
76da22bfc2 zink: track the "real" buffer range from replacement buffers 
when tc replaces a buffer in subdata, it may subsequently perform subdata calls
on the replacement if it is forced to sync during map, e.g.,
* bind_vbo(dst)
* draw
* subdata(src)
  * buffer replacement
  * map
  * tc sync
  * replace_buffer(dst, src)
  * memcpy <- broken
* draw

in this scenario, src may not have data at the time of replacement,
but it will get data soon after, and this buffer range is the real one

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30107>
 2024-07-12 12:29:47 +00:00
Mike Blumenkrantz
fa210726b6 zink: propagate valid buffer range to real buffer when mapping staging 
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30107>
 2024-07-12 12:29:47 +00:00
Danylo Piliaiev
7231eef630 tu: Have single Flush/Invalidate memory entrypoints 
Make all flush/invalidation logic kernel independent. The only
downside is that aarch32 would have cached non-coherent memory
disabled, but there are probably no users of it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11468

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30131>
 2024-07-12 11:48:36 +00:00
Rohan Garg
5bb9c1cca9 anv: reuse existing macro to query for flushes 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30102>
 2024-07-12 10:50:12 +00:00
Eric Engestrom
29c4961b53 v3d/ci: include results of CL run in expectations 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30134>
 2024-07-12 10:12:38 +00:00
Eric Engestrom
10af395f72 v3d/ci: include results of GL full run in expectations 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30134>
 2024-07-12 10:12:38 +00:00
Samuel Pitoiset
aa1f00cf5c nir/gather_info: handle uses_fbfetch_output for texture operations 
Like nir_texop_txf_ms.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30109>
 2024-07-12 09:33:51 +00:00
Samuel Pitoiset
0d0b949cd7 nir/gather_info: handle uses_fbfetch_output for sparse image loads 
Looks like this was missing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30109>
 2024-07-12 09:33:51 +00:00
Samuel Pitoiset
0a6852907d radv: fix marking RADV_DYNAMIC_COLOR_ATTACHMENT_MAP as dirty 
Due to the cmdbuf dirty split.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30119>
 2024-07-12 06:37:52 +00:00
Christian Gmeiner
87786a7a7e nak: Move imad late optimization to nir 
It is more or less just a code move, but I touched
is_only_used_by_iadd(..) to match the style of the other functions in
that file.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30099>
 2024-07-12 05:54:46 +00:00
Christian Gmeiner
e019517d6e nak: Set has_imad32 conditionally 
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30099>
 2024-07-12 05:54:46 +00:00
Faith Ekstrand
b209fedebe nak/sm50: Fix immediates for IMnMx 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
faeb715535 nak/sm50: Re-order all the ops 
This puts them in the same order as nak/ir.rs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
970b3e0e71 nak: Add a legalize() method to ShaderModel 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
e039b7e1ac nak/sm50: Move legalization into SM50Op 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
59f1ad581e nak/sm50: Move instruction encoding into a trait 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
99c4b90f3c nak/sm70: Move legalization into SM70Op 
This puts the legalize routine and the encoder right next to each other
in the code, making it much easier to verify that legalize() enforces
all of the constraints reqauired by encode().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
f20b1c50b4 nak/legalize: Handle RA instructions up-front 
This pulls them out of the per-SM flow.  They're also all no-ops to
legalize since they don't take vectors and are handled directly by RA.
This also means these instructions are now getting properly handled on
Maxwell where we previously trusted in the (probably broken) maxwell
legalizing code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
9d8d928a59 nak/legalize: Handle OpBreak and OpBSSy specially 
This lets us stop passing liveness information into the per-op
legalization code.  Long-term, I want to add a more general core
concept of destinations which are also reads but I haven't gotten
around to that yet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
d9a9bb651c nak/legalize: Move a bunch of helpers to a trait 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
1b9b6a9529 nak/sm70: Re-organize the code a bit 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
20e1160f3f nak/sm70: Move instruction encoding into a trait 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
57667aeac8 nak: Move instruction encoding into ShaderModel 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
d4db2f43de nak: Move Instr::can_be_uniform() into ShaderModel 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
6ddb2b291d nak: Move RegFile::num_regs() into ShaderModel 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
74ac40da2d nak/ra: Move the NAK_DEBUG=spill logic into RA 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
e6b8da5427 nak: Plumb a ShaderModel trait through everywhere 
Instead of scattering number checks everywhere, this lets us actually
start splitting code paths.  This commit just adds the shader model
trait.  Later commits will add more methods.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
69bea2b49f nak/sm50: Get rid of the hand-rolled align_up/down() helpers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
0f7ff6fbdc nak: Move encode_sm* to to sm*.rs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:31 +00:00
Faith Ekstrand
d82a5d0f59 nak/sph: Stop storing the shader model in ShaderProgramHeader 
It's only needed for one Kepler+ check which is unlikely to ever be
relevant for NAK.  Also, that should probably be based on the SPH
version or something, not an arbitrary shader model.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>
 2024-07-11 22:28:30 +00:00
Caio Oliveira
c2d1e10315 intel/brw: Don't print extra newlines in assembler 
Handle '\n' when inside the MSGDESC start condition,
otherwise the lexer would apply its default rule (write
to stdout).

Without that, newlines were "leaking" to the output when
parsing a multiple line "MsgDesc". E.g. given the file
example.asm below

```
send(8)  nullUD  g126UD  nullUD  0x02000000  0x00000000
    thread_spawner MsgDesc:  mlen 1 ex_mlen 0 rlen 0
    { align1 WE_all 1Q @1 EOT };
```

the assembler would produce one extra newline

```
$ brw_asm -t hex -g tgl example.asm

31 01 03 80 04 00 00 00 0c 7e 00 70 00 00 00 00
```

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30100>
 2024-07-11 21:07:54 +00:00
Alyssa Rosenzweig
b8dcbfbd39 zink: print pipeline stats for compute shader-db 
this is useful for evaluating compute shaders with zink. the open shader-db
doesn't have any compute shaders in it, but shader-db runner is capable of
compute and we need to handle it. (Rob's shaderdb definitely has some compute
shaders in it, at least.)

this gets us pipeline stats printing on zink+nvk for a simple compute shader I wrote when working on common NIR stuff:

b.shader_test - type: compute, Code Size: 752, Number of GPRs: 19, SLM Size: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30135>
 2024-07-11 20:37:38 +00:00
Alyssa Rosenzweig
8c597c0861 zink: move print_pipeline_stats 
we need it higher up in the file for the next patch. nfc.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30135>
 2024-07-11 20:37:38 +00:00
Louis-Francis Ratté-Boulianne
2b8eaf3bd6 panfrost: add PAN_AFRC_RATE env var to force a compression rate 
Valid values are "default" and integers from 1 to 12 (bpc).

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
2ff543f3b8 panfrost: add support for fixed-rate compression 
Add support for the gallium interface to retrieve supported bitrates
and modifiers and creation of a compressed resource.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
6665840929 panfrost: add translation between modifier and compression rates 
Add some util methods to be able to translate from an AFRC modifier
to the associated compression bitrate (bits-per-components) and
vice-versa. Also add a method to query all the supported compression
bitrate for a format.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
894657a5ed panfrost: add support for AFRC modifiers 
Add support for all three block sizes (16, 24 and 32) and two
paging tiles layout (rotation or scan optimized). The size of the
resource is aligned to the paging tile width and height.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
450c853f8b panfrost: add support for AFRC render targets 
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
df226c237e panfrost: add support for AFRC textures 
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
87aad0a5e4 panfrost: encode component order as an inverted swizzle (v10) 
v10 restricts component orders when AFRC is in use, so we use the
same solution as for AFBC on v7.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
2dae926850 panfrost: add utils for AFRC fixed-rate support 
There are mainly two parameters to control the fixed-rate
compression:

 - Block size: the size (16, 24 or 32 bytes) that will take a
               coding unit (format dependent).
 - AFRC format: the pixel format and paging tile layout

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
fb95e8ada0 panfrost: add device querying for AFRC support 
As of now, only Mali-G310 supports ARM fixed-rate compression but
it should be advertised in bit 25 of TEXTURE_FEATURES_0

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
Louis-Francis Ratté-Boulianne
a7b489f7be panfrost: Add AFRC overlay in v10 xml specification 
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28813>
 2024-07-11 19:02:50 +00:00
David Rosca
6cc32c609b radeonsi/vcn: Add low latency encode support 
This feature should be enabled for use cases when the lowest encoding
latency is desired, such as real-time game streaming.
Disabled by default due to increased power usage.

There is no libva interface currently that could be used for this, so
for now it can only be enabled by setting AMD_DEBUG=lowlatencyenc
environment variable.

See: https://gitlab.freedesktop.org/drm/amd/-/issues/3336

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30039>
 2024-07-11 18:33:41 +00:00
David Rosca
c06b944398 radeonsi: Add debug option to enable low latency encode 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30039>
 2024-07-11 18:33:41 +00:00
Caio Oliveira
e63b0571bc intel/brw: Account for reg_unit() in assembler 
Use reg_unit() to match the internal representation in brw_reg.
Fixes the assembler tool when targetting Xe2.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30060>
 2024-07-11 16:38:54 +00:00
Caio Oliveira
6cdd56e7ed intel/brw: Use brw_inst_set_group() to set QtrCtrl and NibCtrl 
The function handles the Xe2 case where NibCtrl is gone.  Also add
error messages for invalid input when assembling for Xe2, e.g. "2N".

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30060>
 2024-07-11 16:38:54 +00:00