nak: Move RegFile::num_regs() into ShaderModel

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30141>

src/nouveau/compiler/nak/assign_regs.rs

@@ -1316,7 +1316,7 @@ impl Shader<'_> {
         let spill_files =
             [RegFile::UPred, RegFile::Pred, RegFile::UGPR, RegFile::Bar];
         for file in spill_files {
-            let num_regs = file.num_regs(self.sm.sm());
+            let num_regs = self.sm.num_regs(file);
             if max_live[file] > num_regs {
                 f.spill_values(file, num_regs);
 
@@ -1341,7 +1341,7 @@ impl Shader<'_> {
             // texture ops and another 2 for parallel copy lowering
             18
         } else {
-            RegFile::GPR.num_regs(self.sm.sm())
+            self.sm.num_regs(RegFile::GPR)
         };
         if total_gprs > max_gprs {
             // If we're spilling GPRs, we need to reserve 2 GPRs for OpParCopy
@@ -1370,7 +1370,7 @@ impl Shader<'_> {
             if file == RegFile::GPR {
                 gpr_limit
             } else {
-                file.num_regs(self.sm.sm())
+                self.sm.num_regs(file)
             }
         });
 

src/nouveau/compiler/nak/ir.rs

@@ -144,51 +144,6 @@ impl RegFile {
         }
     }
 
-    pub fn num_regs(&self, sm: u8) -> u32 {
-        match self {
-            RegFile::GPR => {
-                if sm >= 70 {
-                    // Volta+ has a maximum of 253 registers.  Presumably
-                    // because two registers get burned for UGPRs? Unclear
-                    // on why we need it on Volta though.
-                    253
-                } else {
-                    255
-                }
-            }
-            RegFile::UGPR => {
-                if sm >= 75 {
-                    63
-                } else {
-                    0
-                }
-            }
-            RegFile::Pred => 7,
-            RegFile::UPred => {
-                if sm >= 75 {
-                    7
-                } else {
-                    0
-                }
-            }
-            RegFile::Carry => {
-                if sm >= 70 {
-                    0
-                } else {
-                    1
-                }
-            }
-            RegFile::Bar => {
-                if sm >= 70 {
-                    16
-                } else {
-                    0
-                }
-            }
-            RegFile::Mem => RegRef::MAX_IDX + 1,
-        }
-    }
-
     fn fmt_prefix(&self) -> &'static str {
         match self {
             RegFile::GPR => "r",
@@ -6325,6 +6280,7 @@ pub struct ShaderInfo {
 
 pub trait ShaderModel {
     fn sm(&self) -> u8;
+    fn num_regs(&self, file: RegFile) -> u32;
 }
 
 pub struct Shader<'a> {

src/nouveau/compiler/nak/sm50.rs

@@ -22,6 +22,18 @@ impl ShaderModel for ShaderModel50 {
     fn sm(&self) -> u8 {
         self.sm
     }
+
+    fn num_regs(&self, file: RegFile) -> u32 {
+        match file {
+            RegFile::GPR => 255,
+            RegFile::UGPR => 0,
+            RegFile::Pred => 7,
+            RegFile::UPred => 0,
+            RegFile::Carry => 1,
+            RegFile::Bar => 0,
+            RegFile::Mem => RegRef::MAX_IDX + 1,
+        }
+    }
 }
 
 impl Src {

src/nouveau/compiler/nak/sm70.rs

@@ -16,12 +16,45 @@ impl ShaderModel70 {
         assert!(sm >= 70);
         Self { sm }
     }
+
+    fn has_uniform_alu(&self) -> bool {
+        self.sm >= 75
+    }
 }
 
 impl ShaderModel for ShaderModel70 {
     fn sm(&self) -> u8 {
         self.sm
     }
+
+    fn num_regs(&self, file: RegFile) -> u32 {
+        match file {
+            RegFile::GPR => {
+                // Volta+ has a maximum of 253 registers.  Presumably
+                // because two registers get burned for UGPRs? Unclear
+                // on why we need it on Volta though.
+                253
+            }
+            RegFile::UGPR => {
+                if self.has_uniform_alu() {
+                    63
+                } else {
+                    0
+                }
+            }
+            RegFile::Pred => 7,
+            RegFile::UPred => {
+                if self.has_uniform_alu() {
+                    7
+                } else {
+                    0
+                }
+            }
+            RegFile::Carry => 0,
+            RegFile::Bar => 16,
+            RegFile::Mem => RegRef::MAX_IDX + 1,
+        }
+    }
 }
 
 struct ALURegRef {