Commit Graph

193069 Commits

Author SHA1 Message Date
Lepton Wu 04d26ceb0a llvmpipe: Set "+64bit" for X86_64
Without this, on some "buggy" qemu cpu setup, LLVM could crash
if LLVM detects the wrong CPU type.

Fixes: f92cadccc6 ("llvmpipe: Always using util_get_cpu_caps to get cpu caps for llvm on x86")

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27539>
2024-02-12 22:43:46 +00:00
Danylo Piliaiev 5dd5d4c4b5 tu: Exclude more a7xx regs from stomping
Stomping these regs even for a short time leads to crashes.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev e4631bee61 freedreno/devices: Update magic regs for a7xx
These regs are written by blob, for some of them blob could
write non-zero values. So executing Turnip after blob without
writing these regs could lead to nasty GPU crashes.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev eb1e71e707 freedreno,tu: Move varying interp and varying repl modes to xml
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev 78c843230c tu/a750: Consider vertex attr buff in gmem allocation
A750 added a new optimization - placement of vertex attributes
into GMEM, so part of GMEM is carved out for it and needs to
be considered during GMEM allocations.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Mark Collins 5266815ca9 tu/a7xx: Update CCU layout logic for A7XX
A7XX introduces some changes into the CCU such as having different
amounts of memory per CCU for depth and color and dividing up CCU
control into two registers A7XX_RB_CCU_CNTL and A7XX_RB_CCU_CNTL2
where CNTL2 no longer requires a complete flush to be updated, we
currently don't take advantage of this as any CCU updates set both
registers but it's a potential optimization we can add in the future.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev 98d6d93a82 turnip,ir3/a750: Implement inline uniforms via ldg.k
Inline consts suffer the same issue as driver params, so they also
should be preloaded via preamble. There is special instruction to
load from global memory into consts.

Co-Authored-By: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Connor Abbott 6a744ddebc ir3: Initial support for pushing globals with ldg.k
Add a separate pass which uses the analyze_ubo_ranges machinery to
construct ranges of readonly globals accessed in the shader and push
them to constants in the preamble, using ldg.k if possible. This is
enough to handle inline uniforms in turnip but also provides a base for
OpenCL, although the pass would need further work for that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Connor Abbott 513fa1873c ir3/a7xx: Fix load_global_ir3 with immediate offset
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Connor Abbott 45c71803f9 tu: Add more info to ldg inline uniform path
This will let us push the ldg into the preamble.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev b87b8fdf73 tu: Use SS6_INDIRECT for VS params
a750 has SS6_DIRECT path broken, we should either use UBO lowering
or SS6_INDIRECT path.

It is implemented as INDIRECT load even on a750+ because with UBO
lowering it would be tricky to get const offset for to use in multidraw,
also we would need to ensure the offset is not 0.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev 76e417ca59 turnip,ir3/a750: Implement consts loading via preamble
A750 expects driver params loaded through the preamble, old path
does work but has issues when the same LOAD_STATE is used between
several draw calls (it seems that LOAD_STATE is executed only for
the first draw call).

To solve this we now lower driver params to UBOs and let NIR deal with
them.

Notes:
- VS params are loaded via old path since blob do the same and there
  are no issues observed.
- FDM is not supported at the moment.
- For now driver params data is emitted via CP_NOP because it's tricky
  to allocate space for the data. (It is emitted when we are already in
  sub_cs)

Co-Authored-By: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev 7429ca3115 tu: Use SS6_INDIRECT consts upload path for 3d blits
3d blits used DIRECT consts upload path, which doesn't work
properly on a750+, however uploading them via SS6_INDIRECT
seem to be working.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev 30597970a5 tu/a7xx: Do not preload shaders, HW does it by default
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev ac75edb8c4 tu/a7xx: Correctly set A7XX_HLSQ_UNKNOWN_A9AE.SYSVAL_REGS_COUNT
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev bc6b847017 ir3: Add ldg.k instruction
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:13 +00:00
Danylo Piliaiev ad52f92cb8 tu: Define and set to zero all SP_*_VGPR_CONFIG regs
SP_FS_VGPR_CONFIG was found to be correlated with blob using avgs/uvgs.
Other SP_*_VGPR_CONFIG where undefined per-stage regs and it was tested
via rddecompiler that they "fix" hangs in respective shader stage,
when such stage uses the following instructions pattern:

  avgs.s.1.tex.0
  (ss) avgs.e;
  uvgs.s.tex.0;
  uvgs.e

The exact meaning of SP_*_VGPR_CONFIG is to be investigated.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:12 +00:00
Jonathan Marek c166c5100b tu/a750: Basic a750 support
Could run vkcube.

Based on changes from Jonathan Marek <jonathan@marek.ca>

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:12 +00:00
Danylo Piliaiev cdadead230 tu/a7xx: Make A7XX_RB_UNKNOWN_8E06 value configurable per-gen
It is some kind of DBG register which has different value
on different gens.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26934>
2024-02-12 22:05:12 +00:00
Sagar Ghuge 98b62434bd intel/compiler: Lower texture operation to combine LOD and AI
We have to push the lowering of texture operations a bit further in
pipeline since nir_lower_tex gets invoked twice and if there is no LOD
source present, nir_lower_tex adds that as a source. Once that's all
done we can easily combine the LOD and array index into a single 32-bit
value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge c984d6e2fc nir: Drop intel specific lowering code
In previous patches, we have moved the Intel specific lowering code in
brw_nir_lower_texture file. We can go ahead and drop the Intel specific
texture source too.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge 15129c7634 intel/compiler: Use nir_tex_src_backend1 to pack LOD and array index
Since this lowering is totally Intel specific, we don't have to
introduce the new texture source. We can use the nir_tex_src_backend1
source to pack LOD/LOD Bias and array index into 32 bit single value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Sagar Ghuge 73a3257968 intel/compiler: Add texture operation lowering pass
This pass combines the LOD or LOD bias and array index into a single
32-bit value since Xe2+ sampler messages requires us to do that.

v2: (Alyssa)
- Use nir_iand_imm instead of nir_iand and nir_imm_int
- Use nir_trim_vector instead of nir_swizzle

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27458>
2024-02-12 21:25:48 +00:00
Lionel Landwerlin 646a7c864d anv: re-introduce BO CCS allocations
On Gfx12.0, CCS allocations have to be allocated per image because the
format of the image goes into the AUX-TT PTEs. The effect on memory
allocations is limited since the main surface granularity in the
AUX-TT PTE is 64KB.

On Gfx12.5, the granularity of the AUX-TT PTE is 1MB. This creates a
lot of waste in the application memory allocations. Fortunately the HW
doesn't care about the format put into the PTEs anymore. So it becomes
possible to have 2 images share the same PTE.

To implement this we bring back an earlier version of AUX-TT mappings
where we used to allocate additional CCS space at the end of the
VkDeviceMemory objects. On Gfx12.5, if the BO has additional CCS
space, we will now map the main surface to that space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin bd197c6bcf intel/aux_map: add helper to compute offset in aux data
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin c0889a127b intel/aux_map: add BSpec reference
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin da6484a8a4 anv: use address helper to compute address u64 value
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin 7763e75eea anv: move ALLOC_HOST_CACHED_COHERENT as define
That way gdb can decode the other flags when looking at the variables.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin 3f64ec141e isl: add a no-aux-align usage flag
This flag signals that the driver will be dealing with aux-tt
alignment requirements on its own.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Lionel Landwerlin 44515bb92c isl: printout sparse usage
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26822>
2024-02-12 21:00:27 +00:00
Rhys Perry 926d9f1cef radv: support minmax filter for more formats
Support should be the same as AMDVLK, except for these formats:
- VK_FORMAT_R4G4_UNORM_PACK8
- VK_FORMAT_A4R4G4B4_UNORM_PACK16_EXT
- VK_FORMAT_A4B4G4R4_UNORM_PACK16_EXT
- VK_FORMAT_A1B5G5R5_UNORM_PACK16_KHR
- VK_FORMAT_A8_UNORM_KHR
- VK_FORMAT_X8_D24_UNORM_PACK32
- VK_FORMAT_D24_UNORM_S8_UINT
And the various emulated compressed formats.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27551>
2024-02-12 20:05:27 +00:00
Faith Ekstrand 05cf04ac97 nvk: Convert shader addresses to offsets in nvk_shader.c
Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Faith Ekstrand afd42f5951 nvk/heap: Rework over-allocation
Instead of making it part of every BO, just reserve a bit of space at
the end of the top buffer as part of setting up our vma_heap.  This
reduces our memory allocation by nvk_heap::overalloc per BO and means
that the over-allocation is taken into account when sparse binding heap
BOs in the contiguous case.

Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Faith Ekstrand 728256e994 nvk/heap: Use nvk_heap_bo::addr instead of bo->offset
Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Faith Ekstrand 83521dd486 nvk: Don't set CONSTANT_BUFFER_SELECTOR with a zero size
Kepler complains about this and it's unnecessary since we set
ENABLE_FALSE whenever we have a zero size anyway.

Fixes: 55413e33dc ("nvk: Disable all cbufs in nvk_queue_init_context_draw_state()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27565>
2024-02-12 18:47:07 +00:00
Sviatoslav Peleshko 28ad2f488a anv: Store host-located copy of NULL surface state for faster memcpy
Real null_surface_state is located in the GPU memory, so copying from
there will be slow for dGPUs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10594
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27577>
2024-02-12 17:48:15 +00:00
Neil Armstrong 48a0a3112f freedreno: Add a750 clock gating control related registers
The A750 doesn't have an HWCFG clock gating control but instead a set
of additionnal RBBM registers, add them to allow setting up hardware clock
gating on the A750 GPU.

Registers definitions are used from [0] and [1].

[0] https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel/-/blob/gfx-kernel.lnx.14.0.r3-rel/gen7_reg.h#L636
[1] https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel/-/blob/gfx-kernel.lnx.14.0.r3-rel/adreno_gen7.c#L490

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27576>
2024-02-12 17:10:09 +00:00
Konstantin Seurer 097e543c0a Revert "zink: always force flushes when originating from api frontend"
This reverts commit 03f049f497.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27560>
2024-02-12 16:47:30 +00:00
Konstantin Seurer aed5e4e1f2 zink: Always set mfence->submit_count to the fence submit_count
Fixes glFinish not finishing all GPU work.

cc: mesa-stable

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8257
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27560>
2024-02-12 16:47:30 +00:00
David Rosca 8d44a11508 radeonsi/vcn: Don't reinitialize encode session on bitrate/fps change
When bitrate or fps change is detected, only update rate control
parameters instead of completely reinitializing encode session.

This fixes an issue where if application changed bitrate or fps often,
the output bitrate would significantly overshoot the target bitrate in some
cases. In other cases, the output bitrate would be extremely low instead.

Cc: mesa-stable

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27548>
2024-02-12 16:00:39 +00:00
Lionel Landwerlin e0b4dfbbda anv: don't unmap AUX ranges at BO delete
It is possible to free memory backing images before images are
destroyed :

   VkFreeMemory:

   "Memory can be freed whilst still bound to resources, but those
    resources must not be used afterwards."

The spec leaves us the option to keep a reference on the associated
memory and free it only when all the bound resources have been
destroyed. Here we choose to free memory immediately.

One particular test in the CTS
(dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics)
does the following :

   imgA = vkCreateImage()
   imgB = vkCreateImage()
   memA = vkAllocateMemory()
   vkBindImageMemory(imgA, memA) # Aux mapping with ref count = 1
   vkFreeMemory(memA)            # Aux mapping removed, ref count = 0
   memB = vkAllocateMemory()     # Same address as memA
   vkBindImageMemory(imgB, memB)
   vkDestroyImage(imgA)	         # Removes the mapping of imgB-memB

   vkQueueSubmit()               # hang with pagefault in AUX-TT

The solution implemented in this change is to not do anything AUX-TT
related in vkFreeMemory(). This soluation has some consequences,
because a virtual memory address range freed and reallocated cannot be
rebound in the AUX-TT until all the associated resources have released
their AUX-TT mapping (to bring back the AUX-TT refcount of the range
to 0). This should still be better than keeping the memory allocated
through refcounting of the anv_bo.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7b87e1afbc ("anv: track & unbind image aux-tt binding")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10528
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27566>
2024-02-12 15:37:18 +00:00
Konstantin Seurer fb62bffcda radv: Wire up ac_gather_context_rolls
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27322>
2024-02-12 14:04:24 +00:00
Konstantin Seurer ba6d6e5ee1 amd/common: Use the correct register table for GFX10_3
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27322>
2024-02-12 14:04:24 +00:00
Timothy Arceri 1098afd7fb gallium: add PIPE_CAP_FP16 for AMD_gpu_shader_half_float
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri 6fbf336788 compiler/types: Add a contains_32bit helper
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri 5f1f6d7496 glsl: add half float AMD_shader_trinary_minmax functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri d619c16c3f glsl: add half float derivative functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri 14de2eff89 glsl: add half float interpolation functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri 9dc5eec02c glsl: allow half float varyings
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00
Timothy Arceri 3dc67c2c7e glsl: add half float vector relational functions
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18540>
2024-02-12 13:23:14 +00:00