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Author SHA1 Message Date
Simon Perretta
05912bcb60 pco: initial legalize pass/validation to handle hw restrictions 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:49 +00:00
Simon Perretta
4402649b01 pco, pygen: track which hw srcs map to op srcs/dests 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:49 +00:00
Simon Perretta
4e171bcf89 pco, pygen: further abstract src/dest references 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:48 +00:00
Simon Perretta
d552d5b278 pco, pygen: add support for bitwise logical ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:48 +00:00
Simon Perretta
c2787d1d12 pco, pygen: add support for unpck and conversions 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:47 +00:00
Simon Perretta
8c379b0c3e pco, pygen: add support for dma ld and add64_32 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:47 +00:00
Simon Perretta
ff51ba7e43 pco, pygen: add support for tst, movc instructions and s{lt,ge,eq,ne} ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:47 +00:00
Simon Perretta
f1b63fe3f9 pco, pygen: add fdiv/frcp support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:46 +00:00
Simon Perretta
7fb0223c93 pco, pygen: support enum mappings for instances of two bitsets 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:46 +00:00
Simon Perretta
88ac50cbb2 pco, pygen: amend translation of srcs/dests with no mods 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:45 +00:00
Simon Perretta
e9c7afc217 pco, pygen: rework isa gen to support multi-instruction groups 
- Split encode and group mappings to allow the former to be re-used.
- Add custom zero value mapping for bitset enums.
- Enable optional enum mapping for ref mods (previously just op mods).
- Commonize nop/nop.end.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:45 +00:00
Simon Perretta
11238774a4 pco: amend z/w usage code 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:45 +00:00
Simon Perretta
6ca0f828fa pco: amend source validation tracking 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:44 +00:00
Simon Perretta
18ef63e365 pco: drop shader binary finalizing 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:44 +00:00
Mel Henning
b9a9f6cd53 meson: Allow unnecessary_transmutes for bindgen 
Otherwise I get hundreds of "unnecessary transmute" warnings
on rustc 1.88.0

Cc: mesa-stable
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35874>
 2025-07-08 20:51:44 +00:00
Luigi Santivetti
0eb67508bd vulkan/util: add vk_realloc2 
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35998>
 2025-07-08 20:22:13 +00:00
Sviatoslav Peleshko
8d22eb960b brw/disasm: Fix Gfx11 3src-instructions dst register disassembly 
The conversion from bit value to register file type is already done
by the brw_eu_inst_3src_a1_dst_reg_file in the FFC macro now, so doing it
again produced incorrect results.

Fixes: e7179232 ("intel/brw: Move encoding of Gfx11 3-src inside the inst helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13141
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35960>
 2025-07-08 19:49:09 +00:00
Rob Clark
5b619cc4b0 freedreno: Advertise external_only if we can't render 
Don't claim we can render to formats unconditionally.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:45 +00:00
Rob Clark
29c342649d freedreno: Avoid unnecessarily aligning to gmem_align_w 
If we aren't going to be rendering to this resource, we don't need to
take gmem alignment into account.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:45 +00:00
Rob Clark
70fe77f61b freedreno/a6xx: Allow suboptimal sampling formats when requested 
We prefer PoT block sizes for various reasons, but if we are asked to
import 12/24/48b formats for sampling we can do so.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:45 +00:00
Rob Clark
63b33eb4d9 dri: Correct handle-usage flags 
If we can only import for sampling from, don't tell the driver that we
want to render to the handle.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:43 +00:00
Rob Clark
ba7454a155 dri2+gallium: Support to import suboptimal formats 
In some cases a format may be supported in a more limited way by the
hardware.  For example, formats with NPoT pixel sizes.  A driver might
normally prefer that mesa/st use R8G8B8X8 rather than R8G8B8.  But if
the user wants to (dma-buf/etc) import R8G8B8, it is still possible,
and in this case zero copy is more important.

So add a PIPE_BIND_x flag as a hint to the driver when checking if
a format is supported.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:43 +00:00
Petar G. Georgiev
2870addd15 freedreno/fdl: Add support for RGB888/BGR888 pipe formats in render buffer creation 
This enables the rendering of RGB/BGR 24-bit format buffers directly
onto the framebuffer. For RGB888, support already exists for vertex and
texture formats, so render buffer format support has been added. For
BGR888, support for vertex, texture, and render buffer formats has been
added. The internal format chosen for both RGB888 and BGR888 is GL_RGB8.

Change-Id: I0557389dba05d3b44d7b935f02683df17e41fbd2
Signed-off-by: Petar G. Georgiev <quic_petarg@quicinc.com>
Signed-off-by: Lakshman Chandu Kondreddy <quic_lkondred@quicinc.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:43 +00:00
Rob Clark
67a980ee95 freedreno/layout: Support for NPoT formats 
Three component formats don't get UBWC, but do get their pitch aligned
to the next PoT size.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:43 +00:00
Rob Clark
34b61a23d2 freedreno/a6xx: Don't try to tile NPoT formats 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:43 +00:00
Konstantin Seurer
02d0b6bfa6 llvmpipe: Allocate some stuff on demand 
The memory footprint of the table has gotten quite out of hand (>3GB in
Control DX12). This patch brings that number down to around 3MB.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35959>
 2025-07-08 18:22:12 +00:00
Konstantin Seurer
da1c8f6373 llvmpipe: Move allocation out of compile_sample_functions 
Makes it much more clear what is happening.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35959>
 2025-07-08 18:22:12 +00:00
Alyssa Rosenzweig
5270b65d3e agx: lower alu after scalarizing 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989>
 2025-07-08 17:09:16 +00:00
Alyssa Rosenzweig
fc95397957 nir/lower_alu: optimize min/max signed zeros 
we don't usually need a multi-instruction lowering.

with the agx change in the next commit, honeykrisp results:

   Totals from 3589 (6.64% of 54019) affected shaders:
   MaxWaves: 3598144 -> 3598400 (+0.01%); split: +0.02%, -0.01%
   Instrs: 1445830 -> 1332394 (-7.85%)
   CodeSize: 10696356 -> 9742130 (-8.92%)
   Fills: 721 -> 723 (+0.28%); split: -0.14%, +0.42%
   Scratch: 3980 -> 3968 (-0.30%)
   ALU: 1156426 -> 1043198 (-9.79%)
   FSCIB: 1156426 -> 1043196 (-9.79%)
   IC: 267202 -> 267166 (-0.01%)
   GPRs: 208765 -> 208712 (-0.03%); split: -0.16%, +0.14%
   Uniforms: 683643 -> 683677 (+0.00%); split: -0.01%, +0.01%
   Preamble instrs: 1163325 -> 1159314 (-0.34%)

control results alone:

   Totals:
   Instrs: 110168 -> 107171 (-2.72%)

   Totals from 71 (22.26% of 319) affected shaders:
   Instrs: 48895 -> 45898 (-6.13%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989>
 2025-07-08 17:09:16 +00:00
Alyssa Rosenzweig
042adf3cc5 nir/opt_algebraic: optimize signed pow in Control 
used in a post-processing shader which goes 896 instrs -> 749 instrs.

In my Control fossil:

   Totals from 2 (0.63% of 319) affected shaders:
   Instrs: 2078 -> 1841 (-11.41%)
   CodeSize: 14540 -> 12800 (-11.97%)
   ALU: 1779 -> 1626 (-8.60%)
   FSCIB: 1779 -> 1626 (-8.60%)
   Uniforms: 370 -> 372 (+0.54%)

In radv_fossils, there are affected shaders in Dredge.

   Totals from 4 (0.01% of 54019) affected shaders:
   Instrs: 2306 -> 2294 (-0.52%)
   CodeSize: 16594 -> 16534 (-0.36%)
   ALU: 2010 -> 2004 (-0.30%)
   FSCIB: 2010 -> 2004 (-0.30%)
   Uniforms: 1138 -> 1146 (+0.70%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989>
 2025-07-08 17:09:16 +00:00
Alyssa Rosenzweig
2765017553 nir: fuse ffma even with float controls 
The fmul+fadd -> fma rules in nir_opt_algebraic are marked imprecise,
because they are a contraction. However, they respect signed zero/Inf/NaN rules.
As such, it is legal to do this fusion with shader float controls as long as the
exact bit is not set (mapping to SPIR-V NoContract).

Unfortunately, NIR's imprecise rules do not distinguish between contraction
issues versus float special case issues, forcing nir_search to skip all
imprecise rules when any shader float control modes are used. This notably
affects DXVK, which sets shader float controls to get D3D11 float behaviour and
hence loses FMA fusing.

Therefore, we plumb in the exact bit to express NoContract independent of the
float controls, and weaken the requirement for fma fusion to allowable
contraction. For fma splitting, it's a similar issue, as inexact GLSL fma in
SPIR-V is just a multiply add that we're allowed to contract rather than the
real deal.

Drivers that use their own FMA fusing passes (notably, Intel and AMD) are
unaffected, but DXVK-capable drivers using fuse_ffma should like this. Results
on hk shown:

Totals from 2194 (4.06% of 54019) affected shaders:
MaxWaves: 2174272 -> 2175936 (+0.08%); split: +0.08%, -0.01%
Instrs: 1173283 -> 1131494 (-3.56%); split: -3.57%, +0.01%
CodeSize: 8568168 -> 8381724 (-2.18%); split: -2.18%, +0.01%
Spills: 1094 -> 747 (-31.72%)
Fills: 988 -> 681 (-31.07%)
Scratch: 4444 -> 3820 (-14.04%)
ALU: 953032 -> 913149 (-4.18%); split: -4.19%, +0.01%
FSCIB: 953032 -> 913149 (-4.18%); split: -4.19%, +0.01%
IC: 215398 -> 215274 (-0.06%)
GPRs: 139865 -> 139032 (-0.60%); split: -1.56%, +0.96%
Uniforms: 414886 -> 414466 (-0.10%); split: -0.14%, +0.04%
Preamble instrs: 646398 -> 644017 (-0.37%); split: -0.43%, +0.07%

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35989>
 2025-07-08 17:09:16 +00:00
Daniel Schürmann
2c51a8870d nir: add nir_vectorize_cb callback parameter to nir_lower_phis_to_scalar() 
Similar to nir_lower_alu_width(), the callback can return the
desired number of components for a phi, or 0 for no lowering.

The previous behavior of nir_lower_phis_to_scalar() with lower_all=true
can be elicited via nir_lower_all_phis_to_scalar() while the previous
behavior with lower_all=false now corresponds to nir_lower_phis_to_scalar()
with NULL callback.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35783>
 2025-07-08 15:33:59 +00:00
Daniel Schürmann
23b7b3b919 nir/lower_phis_to_scalar: remove exec_list dead_instrs 
No need to free the instructions at this point.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35783>
 2025-07-08 15:33:59 +00:00
Daniel Schürmann
f6e0f4813c nir: remove recursive check in nir_lower_phis_to_scalar() 
This check causes unnecessary overhead and can be replaced by simply
checking whether a phi_src is from a loop continue block.
Except for rare edge cases, the result will be the same.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35783>
 2025-07-08 15:33:59 +00:00
Corentin Noël
8c96b9b9c7 virgl: Add more Gallium formats to the list 
Include the recently added formats.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35908>
 2025-07-08 15:14:37 +00:00
Pohsiang (John) Hsu
5c1f45a21b mediafoundation: fix cropping flag when using software sample 
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35981>
 2025-07-08 14:50:29 +00:00
Pohsiang (John) Hsu
42674c0df1 mediafoundation: make file version the same as product version, and increment version to 1.0.6 
for 1.0.5 release, File version was showing 1.0.0.0 and Production version was showing 1.0.5.0.
now both show 1.0.6.0.

Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35981>
 2025-07-08 14:50:28 +00:00
Valentine Burley
fd073bc1c3 zink/ci: Update restricted trace checksums 
These changed with b61e6b9748 ("zink: enable ioopt by default").

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36003>
 2025-07-08 14:34:42 +00:00
Marek Olšák
656675a490 nir: change nir_lower_mem_access_bit_sizes to an intrinsics pass 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35999>
 2025-07-08 14:01:56 +00:00
Marek Olšák
1cc5f7f868 nir: add nir_shift_channels helper 
for later use

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35999>
 2025-07-08 14:01:56 +00:00
Marek Olšák
5760f92e08 nir: print lowp/mediump/highp next to deref types 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35999>
 2025-07-08 14:01:56 +00:00
Marek Olšák
070aaa1c9f nir/lower_io: validate that location and num_slots fit in the bitfields 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35999>
 2025-07-08 14:01:56 +00:00
Marek Olšák
5aa3748b26 nir: remove deprecated nir_io_dont_optimize 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35999>
 2025-07-08 14:01:56 +00:00
Marek Olšák
dd06c24577 gallium/noop: fix a crash in sampler_view_release 
This fixes running shader-db with GALLIUM_NOOP, which is good for
measuring only GLSL/frontend compile times.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35995>
 2025-07-08 13:39:15 +00:00
Gert Wollny
3b27269be4 mesa/st: Re-instate test for shader_clock cap 
With the check for the cap gone no driver will expose
ARB_shader_clock. Unfortunately the CI doesn't catch this
because it doesn't provide expectations whether a test should
pass or be skipped. In this case

  spec@arb_shader_clock@execution@clock
  spec@arb_shader_clock@execution@clock2x32

went from pass to skip. (Tested on r600, but on radeonsi one
can also see that the extension ARB_shader_clock is no longer
available).

Adding the test for the cap back in fixes this.

Fixes: 2ce201707e (Add support for EXT_shader_clock)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35992>
 2025-07-08 12:47:31 +00:00
Mel Henning
7e2ff0a35c nak/nvdisasm_tests: Remove extra . for lod_mode 
Fixes: cb9e458d29 ("nak: Rework printing of TexLodMode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35994>
 2025-07-08 12:27:02 +00:00
Mike Blumenkrantz
df0c25610e st/clear: handle null color renderbuffer 
Fixes: 2eb45daa9c ("gallium: de-pointerize pipe_surface")

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35973>
 2025-07-08 11:50:41 +00:00
Christoph Pillmayer
0dd73981b2 panvk: Fix IUB desc type check 
Fixes: 2ec6527c70 ("panvk: Implement VK_EXT_inline_uniform_block")

Reviewed-by: John Anthony <john.anthony@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35969>
 2025-07-08 10:49:15 +00:00
jesse.zhang
56d758d321 amd: Add user queue HQD count to hw_ip info 
Add a new field userq_num_hqds to drm_amdgpu_info_hw_ip to expose the
number of available hardware queue descriptors (HQDs) for user queues.
This allows userspace to query the maximum number of user queues that
can be created for a particular IP block.

the patch link in driver side:
https://lists.freedesktop.org/archives/amd-gfx/2025-June/126686.html

v2: we should also put userq_num_hqds into radeon_info and
print it where other fields are printed. (Marek Olšák)

v3: rename num_userqs to num_queue_slots
    and add print log in ac_print_gpu_info. (Marek Olšák)
v4: rename userq_num_hqds to userq_num_slots in hw_ip_info,
    and update the hw information (Marek Olšák)

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35850>
 2025-07-08 10:17:51 +00:00
Calder Young
a39779e695 iris: Fix issue with conditional dispatching 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35946>
 2025-07-08 10:00:45 +00:00