b07c215c35
intel: fix URB programming for GT1s
...
We're missing a programming restriction.
Hopefully fixing
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on
Gfx9atoms
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6216
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >.
Tested-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596 >
2022-04-17 21:24:17 +00:00
1407a4db69
intel/batch-decoder: Fix uninitialized scalar variables
...
CID: 1498516
CID: 1498560
Signed-off-by: Vitalii Lomaka <vitalii.lomaka@globallogic.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15685 >
2022-04-08 18:35:34 +00:00
9bc97e4fc1
intel/decoder: Fix decoder handling of binding table pool alloc on XeHP
...
3DSTATE_BINDING_TABLE_POOL_ALLOC no longer has a "Binding Table Pool
Enable" bit. It is always enabled.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15625 >
2022-03-29 02:35:54 -07:00
3bd9b25060
intel: change INTEL_MEASURE output to microseconds
...
Change time event durations from ns -> us. Microseconds are easier
to work with.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
2e6d14cc7b
intel: increase INTEL_MEASURE batch/buffer sizes
...
Increase default batch_size and buffer_size from 16 -> 64. These
are sized to be big enough to service most games. As games have
become more demanding, larger sizes become necessary.
Reviewed-by: Mark Janes <markjanes@swizzler.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15348 >
2022-03-17 22:14:42 +00:00
12d815bcac
intel/guardband: Take min/max instead of total size
...
Reviewed-by: Ivan Briano <ivan.briano@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14961 >
2022-03-16 13:13:45 -05:00
dbcdededb2
intel: Add missing dep of gen_*_header.py on utils.py.
...
Reviewed-by: Dylan Baker <dylan@pnwbakers.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725 >
2022-02-02 11:21:57 -08:00
c93cbc77f7
intel/common: Add helper for URB allocation in Mesh pipeline
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
b01c73fd0a
intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
...
And corresponding value in XML.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662 >
2022-02-02 18:17:57 +00:00
8599ded193
intel: Only reserve space for Compute Engine out of URB in Gfx12LP
...
Reviewed-by: Francisco Jerez <currojerez@riseup.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14756 >
2022-01-28 14:52:17 -08:00
79b199b333
intel: Allow copy engine class in intel_gem_create_context_engines()
...
I want to use I915_ENGINE_CLASS_COPY in iris.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687 >
2022-01-24 23:27:25 +00:00
695ba644ab
intel/gem: Return length from intel_i915_query_alloc
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13866 >
2022-01-19 00:29:35 +00:00
69df00b33b
intel/ds: reuse intel_ioctl()
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13996 >
2022-01-14 20:17:44 +00:00
14a4600b62
intel: add swizzle flag into driver uuid
...
Suggested by Lionel Landwerlin, we add has_bit6_swizzle as
another input when computing driver uuid.
Also fix miscalculation of the length of driver tag.
Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936 >
2022-01-13 03:09:36 +00:00
d86989bf73
intel: use PCI info to compute device uuid
...
With the new input from PCI bus and device fields, we can compute
device uuids in a multi-gpu system.
Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Rohan Garg <rohan.garg@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936 >
2022-01-13 03:09:36 +00:00
074bde9989
intel/xehp: Switch to coarser cross-slice pixel hashing with table permutation.
...
The coarser 32x32 cross-slice hashing mode seems to lead to better L1
and L2 utilization due to the improved execution locality, however it
can also lead to a bottleneck in a single slice, especially in
workloads that concentrate heavy rendering in small areas of the
screen (e.g. SynMark2 OglGeomPoint, OglTerrain*) -- This effect is
mitigated here by performing a permutation of the pixel pipe hashing
tables that ensures that adjacent rows map to pixel pipes as far away
as possible in the caching hierarchy.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
283d5bff4e
intel: Rename intel_compute_pixel_hash_table() to intel_compute_pixel_hash_table_3way().
...
For consistency with intel_compute_pixel_hash_table_nway().
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
170468b4fe
intel: Minimal calculation of pixel hash table for arbitrary number of pixel pipes.
...
This starts off with the simplest possible pixel hashing table
calculation that just assigns consecutive indices (modulo N) to
adjacent entries of the table, along the lines of the existing
intel_compute_pixel_hash_table(). The same function will be improved
in a future commit with a more optimal calculation.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
68cb551b1d
intel: Move pixel hashing table computation into common header file.
...
In order to avoid some duplication between the GL and Vulkan driver,
which will get worse as we introduce additional code in order to
handle more recent generations.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569 >
2022-01-10 18:28:35 -08:00
fd2a558bf8
intel/l3: Make DG1 urb-size exception more generic
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14136 >
2021-12-11 00:09:50 +00:00
d051854cca
treewide: drop mtypes/macros includes from main
...
These aren't required in lots of places, so remove them.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14127 >
2021-12-08 22:14:45 +00:00
0634cb741b
intel: Add intel_gem_create_context_engines
...
Engines based contexts operate somewhat different for executing
batches. Previously, we would specify a bitmask value such as
I915_EXEC_RENDER to specify to run the batch on the render ring.
With engines contexts, instead this becomes an array of "engines", and
when the context is created we specify the class and instance of the
engine.
Each index in the array has a separate hardware-context. Previously we
had to create separate kernel level contexts to create multiple
hardware contexts, but now a single kernel context can own multiple
hardware contexts.
Another forward looking advantage to using the engines based contexts
is that the kernel does not plan to add new supported I915_EXEC_FOO
masks, whereas they instead plan to add new I915_ENGINE_CLASS_FOO
engine classes. Therefore some rings may only be usable with an engine
based class.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12692 >
2021-12-02 16:30:38 -08:00
9a9042a904
intel: Add intel_gem_count_engines
...
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12692 >
2021-12-02 16:30:31 -08:00
29c2f32a57
intel/dev: Add platform enum with DG2 G10 & G11
...
Based on Lionel's "intel/devinfo: store the different kind of DG2".
Ref: 361b3fee3chttps://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e22cfc5e9b92556a56d8a564cdab31045f29010
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13797 >
2021-11-15 21:39:27 +00:00
361b3fee3c
intel: move away from booleans to identify platforms
...
v2: Drop changes around GFX_VERx10 == 75 (Luis)
v3: Replace
(GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
by
(devinfo->platform == INTEL_PLATFORM_IVB)
Replace
(devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
by
(devinfo->verx10 >= 45)
Replace
(devinfo->platform != INTEL_PLATFORM_G4X)
by
(devinfo->verx10 != 45)
v4: Fix crocus typo
v5: Rebase
v6: Add GFX3, ILK & I965 platforms (Jordan)
Move ifdef to code expressions (Jordan)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981 >
2021-11-08 16:48:06 +00:00
bba26939b1
intel/decoder: Dump Task/Mesh shaders
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jordan Justen <jordan.l.justen@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13657 >
2021-11-04 21:01:13 +00:00
e69d395cd1
intel/genxml: Add an "mbz" data type
...
There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.
This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct. We also update the decoder to handle it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480 >
2021-10-28 19:45:55 +00:00
37f03e89f2
intel: Add and use max_constant_urb_size_kb
...
This knowledge was repeated in multiple places so move the values to
intel_device_info struct.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13014 >
2021-09-27 20:51:28 +00:00
929db0a818
intel/decode/gfx6: add support for gfx6 CC/VIEWPORT pointers.
...
These have 3 sub states encoded and valid fields on SNB.
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12864 >
2021-09-16 05:13:16 +10:00
18477f60e2
intel/dg2: Add L3 configuration
...
Rework:
* Jordan: Merge dg1/dg2 into empty_l3_list
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12711 >
2021-09-14 02:51:03 +00:00
ce1a66fe3e
meson/intel: Don't build genxml tests on Android
...
They require expat which we don't have on Android.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com >
Reviewed-by: Eric Engestrom <eric@engestrom.ch >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12308 >
2021-08-11 23:57:52 +00:00
e79a78a16f
intel/decode: add gfx4 vertex shader decode
...
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12160 >
2021-08-02 07:23:58 +10:00
0dec873f2a
intel/decode: add gfx4 constant buffer decode
...
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12160 >
2021-08-02 07:23:38 +10:00
b6843d990b
intel/tools/aubinator_error_decode: tag hanging instruction
...
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11957 >
2021-07-21 08:20:06 +00:00
f5008a48d3
intel/perf: Use intel_i915_query_flags instead of hand-rolling it
...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770 >
2021-07-16 14:19:20 +00:00
ffdf4d7683
intel: Pull anv_i915_query into common code
...
We also add a helper which contains the standard query+alloc+query
pattern used by anv_gem_get_engine_info(). The caller is required to
free the pointer.
These are declared static inline not because we care about the
performance of these helpers but because we're going to use them in the
intel_device_info code and we don't want a link dependency.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11770 >
2021-07-16 14:19:20 +00:00
365c7cc87c
intel/decoder: add assert for register size
...
Coverity complains about out-of-bounds access in
intel_field_iterator_init, because it doesn't know that the GT_MODE
register has a size of 4 bytes. Add an assertion to verify that.
CID: 1474552
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11574 >
2021-06-28 09:31:41 +00:00
f3630548f1
crocus: initial gallium driver for Intel gfx 4-7
...
This is a gallium driver for the Intel gfx 4-7 GPUs.
It was initially cloned from the iris driver by Ilia Mirkin,
then I ported over large reams of code from i965 until it worked.
Acked-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11146 >
2021-06-14 06:34:05 +10:00
4de8ba15b4
intel/decode: handle gen4/5 WM state fragment shaders
...
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11146 >
2021-06-14 06:05:17 +10:00
8e10d54804
intel: Rename GFX 12.5 to XE_HP
...
git grep -l "GFX 12\.5" | xargs sed -ie "s/GFX 12\.5/XE_HP/g"
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10877 >
2021-06-03 15:51:40 -07:00
2c2de4d60e
intel/mi_builder: fix resolve call
...
Giving NULL for anv_combine_address() triggers an assert in that
function.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Fixes: 8525ebe6e3felix.j.degrood@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10301 >
2021-05-13 17:02:41 +00:00
922f71b819
intel/decoder: add gen4/5 geometry state decode
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642 >
2021-05-05 07:28:34 +00:00
d91d3613ad
intel/decoder: fixup batch decoder for binding tables on gen4/5
...
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642 >
2021-05-05 07:28:34 +00:00
10abc09a04
intel: fix MI builder for pre-gen7
...
MI_LOAD_REGISTER_MEM is only available on gen7+, so avoid build errors
on earlier generations.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636 >
2021-05-05 02:56:20 +00:00
4dcfb18a82
intel/decoder: decode CPS_STATE
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455 >
2021-05-02 20:20:06 +00:00
c073648d80
intel/batch_decoder: set foreground color of decoded instructions
...
It's impossible to see the names of instructions if the terminal's
color scheme uses black as foreground. Just set it to white - it
will look good on any color scheme.
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com >
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10341 >
2021-04-21 11:47:45 +00:00
12099d51f6
intel: Rename gen_10 to ver_10
...
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241 >
2021-04-20 20:06:34 +00:00
6b4767d083
intel: Remove devinfo_to_gen() helper function
...
This changes behavior. Now Baytrail will be decoded with the
gen7.xml instead of the gen75.xml. Haswell is the only graphics
hardware generation 75 and Baytrail is closer to Ivybridge
in most ways. (Kenneth Graunke)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241 >
2021-04-20 20:06:34 +00:00
4f42b28cc3
intel: Rename gen_{mapped, clflush, invalidate} prefix to intel_{..}
...
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965
grep -E "gen_" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_\(mapped\|clflush\|invalidate\|shader\)/intel_\1/g"
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241 >
2021-04-20 20:06:34 +00:00
726d9696dd
intel: Rename gen_get_device prefix to intel_get_device
...
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_get_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_get_device/intel_get_device/g"
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com >
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241 >
2021-04-20 20:06:34 +00:00
Lionel Landwerlin