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Alyssa Rosenzweig 013bb50168 panfrost: Lower point sprites on Bifrost 
Use the common pass. This only should trigger when drawing points, so we need
some extra tracking to ensure this.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig b6909ebb36 panfrost: Refactor variant rebind code 
For point sprite lowering on Bifrost and Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig 39788ac703 panfrost: Refactor variant selection code 
Extract the "compile a new variant" routine from the "select and bind a variant"
routine. This allows us to simplify the control flow, eliminating the `compiled`
boolean on the shader structure.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig 755f30fb18 panfrost: Simplify shader key architecture 
Rather than clever key compare/initialize code, let's make the shader keys plain
old data. This makes it easier both to extend and to optimize the shader keys.

Keys are compared with a simple memcmp(). I considered a hash table but I don't
think we have enough variants (or large enough keys) to justify the overhead.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig 2c3ed7af53 panfrost: Use s->info.stage instead of tgsi stage 
Now that we have the NIR handy.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig 1c5adbb3df panfrost: Don't subclass pipe_compute_state 
Just copy the bit we need so the NIR doesn't hang around. This is simpler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig b834dea889 panfrost: Call tgsi_to_nir earlier 
This ensures we always have NIR available in the shader state. It also saves a
(trivial) amount of recomputation if multiple TGSI variants are needed.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig 3f505a8bc1 panfrost: Remove ancient unused code 
Leftover scraps.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
 2022-05-02 09:55:49 -04:00
Alyssa Rosenzweig 7864f653ad panvk: Emit fragment RSDs even with no shader 
In Vulkan, it's possible to create a pipeline with no fragment shader that's
still expected to rasterize. This is useful for depth/stencil side effects, and
is closely related to the "fragment shader required" optimization we do in the
GLES driver. Refactor the RSD emit code to handle this case.

Fixes dEQP-VK.pipeline.stencil.nocolor.*

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
 2022-05-02 13:12:31 +00:00
Alyssa Rosenzweig dcf8cdde68 panvk: Gate rasterization on !discard, not fs req 
The "fragment shader required?" computed state is about fragment shader side
effects. There may be no fragment shader required but depth/stencil side effects
meaning that rasterization is nonoptional. What actually gates rasterization is
the rasterizer discard bit. Use that instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
 2022-05-02 13:12:31 +00:00
Alyssa Rosenzweig 6d779412e5 panvk: Streamline no shader RSD case 
Noticed by inspection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
 2022-05-02 13:12:31 +00:00
Alyssa Rosenzweig db7d8519f9 panfrost: Only flip point sprites for GL 
Fixes dEQP-VK.glsl.builtin_var.simple.pointcoord

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
 2022-05-02 13:12:31 +00:00
Alyssa Rosenzweig ba29cdecab panvk: Use correct point size limits 
As determined by Icecream95. Fixes:

dEQP-VK.rasterization.primitive_size.points.point_size_*

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
 2022-05-02 13:12:31 +00:00
Alyssa Rosenzweig 9d84caa4d5 panvk: Ignore point size for !points 
Otherwise wide lines break. The alternative approach is to eliminate the points
writes when not drawing points since we do have topology information at compile
time. I'm admittedly stuck in my GL mindset. That's the approach we'll need for
Valhall anyway.

Fixes dEQP-VK.rasterization.interpolation.basic.lines_wide

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
 2022-05-02 13:12:31 +00:00
Icecream95 2864094f69 pan/bi: Use texture index instead of sampler for message preloading 
The VAR_TEX definition in ISA.xml only has a field for texture_index,
so trying to read sampler_index will return zero; read from
texture_index instead, and rename other fields for consistency.

The texture and sampler indices must be equal for VAR_TEX to be used,
so either name could be used for the field.

Fixes the wrong textures being used in Thief.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6219
Fixes: eb1479bda2 ("pan/bi: Support message preloading")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16255>
 2022-05-02 12:50:44 +00:00
Gert Wollny 4a2ff9eb86 r600: Allow eight bit, three channel formats for vertex buffers 
While using three component texture formats results in CTs failures,
three component vertex attributes are fine, and not allowing them
results in significant performance regressisons.

Fixes: e41958e344
   r600: Disable eight bit three channel formats

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6399

v2: rename function to is_buffer_format_supported (Emma)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16267>
 2022-05-02 12:39:31 +00:00
Lionel Landwerlin 0be9cac742 anv: limit clflush usage 
Discrete platforms don't have LLC, but on those, we mmap our buffers
with WC. So we shouldn't need to clflush there.

Anv already had a boolean field on the physical device to know whether
we need to use clflush(), based off the memory heaps available. So use
that instead.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
 2022-05-02 12:07:01 +00:00
Lionel Landwerlin 44e93b4c6f anv: fix clflush usage on utrace copy batch 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
 2022-05-02 12:07:01 +00:00
Pierre-Eric Pelloux-Prayer 529f316d87 radeonsi: fix VS kill_outputs handling 
981bd8cbe2 moved outputs removing handling to NIR, but instead of
applying it only to the last stage before the FS this now applies
it to both the GS and the VS.

This commit fixes this by clearing the kill_outputs field for
the VS when using a ES-GS shader.

Fixes: 981bd8cbe2 ("radeonsi: apply key.ge.opt.kill_{outputs,pointsize,clipdistance} in NIR")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16249>
 2022-05-02 13:41:39 +02:00
Rhys Perry 8a525c0fa5 radv: consider radix sort shaders to be internal/meta 
Cleans up RADV_DEBUG=shaders

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16198>
 2022-05-02 10:19:23 +00:00
Iago Toral Quiroga c9f68361a8 v3dv: ignore barriers for image layout transitions from undefined layouts 
Layout transitions are not relevant to us, we only care about barriers
that involve a sync point between read/write actions on the image across
GPU jobs.

Image transitions from undefined layout can only happen before the image
is ever used by the GPU, which means they are never relevant to our
implementation.

This improves performance in vkQuake.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga a44d498287 v3dv: document Vulkan requirements for signaling operations 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga 0273f661e6 v3dv: don't emit final noop job if we don't have anything to signal 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga de0d4d671a v3dv: drop obsolete comment 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Iago Toral Quiroga c367bd0ee3 v3dv: ignore no-op barriers 
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
 2022-05-02 08:04:13 +02:00
Alyssa Rosenzweig 31fd926334 agx: Lower mediump flat shading 
This isn't supported by the hardware. Fixes

dEQP-GLES2.functional.shaders.constants.float_uniform_vertex

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 18ef9398de agx: Remove nir_register support 
We don't use it anymore, now that we can handle SSA form. Gets rid of
the most gross hack in the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 3927a9e911 agx: Remove has_liveness 
Given we do no metadata tracking, this is an accident waiting to happen.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 1c6bd0357f agx: Update RA comment 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 6b22bbab36 agx: Add validation pass 
For now, just check that we didn't botch the structure of the block,
since this just bit me.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4498799822 agx: Remove identity moves 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig c712043b9c agx: Unit test parallel copy lowering 
It's pretty tricky.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 6a4d742369 agx: Always use hash table for extracts 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 860832e41b agx: Split up RA from post-RA lowering 
This allows us to validate results in the middle.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig ea065537cb agx: Lower phi nodes to parallel copies 
Now we have an SSA RA :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig ccb0210761 agx: Don't lower phis in NIR 
We're ready for them now! Just scalarize.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig a8da17f628 agx: Copy prop into phi nodes 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 8ff0a29baf agx: Translate phi nodes 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4791dc9125 agx: Make DCE dumber 
The current DCE pass hits issue around phi nodes. These need to be
solved properly eventually, but for now workaround them by doing
something obviously correct (but suboptimal compile time).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 606d9340f3 agx: Adapt liveness analysis for SSA 
Lifted from nir_liveness.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 590df764d6 agx: Introduce worklist infrastructure 
Using the common NIR stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig e414a8c16f agx: Add agx_after_block_logical helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig a2a947031a agx: Mark the logical ends of blocks 
We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 5be26e8624 agx: Add predecessor index helper 
To order phi sources.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 3f1e926bf4 agx: Use a dynarray for predecessors 
This imposes a fixed ordering, allowing phi sources to be implicitly ordered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig d02e913e95 agx: Remove else optimization 
It will conflict with SSA-based RA and needs to be rewritten to happen
late.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4d79f6ca76 agx: Use extract helper for tex internally 
Allows better optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig 4f78141c77 agx: Emit splits for intrinsics 
This allows optimizing the extracts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig d06394095b agx: Optimize p_split(kill) specially 
Let's make sure these are allocated optimally.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00
Alyssa Rosenzweig e16ad8f443 agx: Lower p_split after RA 
Using existing regalloc infrastructure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
 2022-05-01 22:00:00 -04:00