For whatever reason NXP decided to call the GC3000 in the i.MX6QP a
GC2000+. This being a lie is marked in the IP core by the upper half
of the revision register being all ones. The kernel driver already
fixes the model and revision when it encounters this core, but this
breaks matching in the HWDB, which uses the bogus model/rev from the
core.
Revert the fixup done by the kernel for the lookup in the HWDB.
Fixes: 2192e620bb ("etnaviv: hwdb: Add etna_query_feature_db(..)")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33223>
We need to add a variant of the texld instruction, which is used with a shadow
samper and passed the shadow reference value via src2.
Blob generates such texld's for deqp's GLES3.functional.texture.shadow.2d.* (GC3000).
Fixes spec@arb_depth_texture@texdepth.
Fixes: abe5bd35 ("etnaviv: Switch to isa_assemble_instruction(..)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32926>
The BO list member isn't the head/entrypoint for a list, but is only
to be used to link the BO in various lists, so it should not be
initialized as a list head.
Now that the member is properly NULL initialized, we can use the
proper list_is_linked() function to check if the BO is on any
cache bucket or the zombie list.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32233>
This instruction is used to implement float type conversion. The source type
is defined via src1 immed (0: f32, 1: f16) and the dest type is defined via
the instruction type.
Blob generates such conv's for piglit's tests/cl/program/execute/mad-mix.cl
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30797>
Setting it to the same value as (or higher than) the job timeout
effectively bypasses the safety mechanism.
Let's change it to `job timeout - 5min`.
Fixes: f39ffc6911 ("ci/etnaviv: Get the gc2000_piglit manual job mostly working.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
This bumps the req for everything, but I think that's fine, because one
part restricting to a lower rust version doesn't make much sense as we are
also not doing it generally for C or C++.
This also makes it easier for packagers to know what requires rust.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30414>
COARSE clocks add a worst-case jitter of 10ms to the timing, as they
degrade the timing to Linux jiffy accuracy. However, they allow to skip
a syscall on platforms where the accurate version of the clock can not
be accelerated through the VDSO.
Switch to using the COARSE version of the clock when the timeout is
larger than 200ms, i.e. the accuracy of the timeout is degraded less
than 5% by the added worst-case jitter.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27079>
By using the the COARSE variant of the clock we can avoid a syscall
to fetch the current time on platforms where the more accurate
version of the clock can not be accelerated through the VDSO. The
most relevant platform with this restriction is ARM32 without the
architected timer extension, e.g. the NXP i.MX6.
The COARSE clock degrades the accuracy of the timing to Linux
jiffies, which means it adds a worst-case jitter of 10ms, which is
basically noise in relation to the 1sec holding time of the cache
and the irregular call pattern of etna_bo_cache_cleanup().
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27079>
Introduce unary and binary versions of the branch instruction. This will
give more ISA_OPC_BRANCH_XXX opcodes to work with. This helps to get rid
of these 'maybe' bitsets and is needed for the assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30030>
When there are active PMRs attached to the command buffer we can
not optimize the flush away, as that results in the queries never
reaching their expected sequence number, livelocking readers
waiting for the query result.
Fixes: 148658638e7f ("etnaviv: drm: Be able to mark end of context init")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30055>
An extended instruction uses 0x7f as opcode and stores the extended
opcode in the IMMED of src2.
Reverse engineered with the following dEQPs:
- dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.int_lowp_vertex
- dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.uvec3_lowp_fragment
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30010>
Pavel Ondračka