ci/bare-metal: rename fastboot & cros-servo TEST_PHASE_TIMEOUT to TEST_PHASE_TIMEOUT_MINUTES to be coherent

Avoids the risk of accidentally copy/pasting the wrong variable name
from another baremetal job.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30409>
This commit is contained in:
Eric Engestrom
2024-07-31 09:00:10 +02:00
parent 1e5fb15afa
commit 771e07ad93
4 changed files with 8 additions and 8 deletions

View File

@@ -107,7 +107,7 @@ python3 $CI_INSTALL/custom_logger.py ${STRUCTURED_LOG_FILE} --update-dut-time su
python3 $BM/cros_servo_run.py \
--cpu $BM_SERIAL \
--ec $BM_SERIAL_EC \
--test-timeout ${TEST_PHASE_TIMEOUT:-20}
--test-timeout ${TEST_PHASE_TIMEOUT_MINUTES:-20}
ret=$?
python3 $CI_INSTALL/custom_logger.py ${STRUCTURED_LOG_FILE} --close-dut-job
python3 $CI_INSTALL/custom_logger.py ${STRUCTURED_LOG_FILE} --close

View File

@@ -151,7 +151,7 @@ fi
set +e
$BM/fastboot_run.py \
--dev="$BM_SERIAL" \
--test-timeout ${TEST_PHASE_TIMEOUT:-20} \
--test-timeout ${TEST_PHASE_TIMEOUT_MINUTES:-20} \
--fbserial="$BM_FASTBOOT_SERIAL" \
--powerup="$BM_POWERUP" \
--powerdown="$BM_POWERDOWN"

View File

@@ -86,7 +86,7 @@ gc2000_piglit:
variables:
DEQP_SUITE: etnaviv-gc2000-piglit
FLAKES_CHANNEL: "#etnaviv-ci"
TEST_PHASE_TIMEOUT: 40
TEST_PHASE_TIMEOUT_MINUTES: 40
timeout: 40m
gc7000_gles2:

View File

@@ -20,7 +20,7 @@ a306_piglit:
DEQP_SUITE: freedreno-a306-piglit
HWCI_START_WESTON: 1
JOB_TIMEOUT: 40
TEST_PHASE_TIMEOUT: 40
TEST_PHASE_TIMEOUT_MINUTES: 40
# Something happened and now this hangchecks and doesn't recover. Unkown when
# it started.
@@ -95,7 +95,7 @@ a618_vk_full:
FDO_CI_CONCURRENT: 4
DEQP_SUITE: freedreno-a618-vk-full
JOB_TIMEOUT: 180
TEST_PHASE_TIMEOUT: 180
TEST_PHASE_TIMEOUT_MINUTES: 180
a618_gl:
extends:
@@ -156,7 +156,7 @@ a618_piglit_full:
FLAKES_CHANNEL: "#freedreno-ci"
HWCI_START_WESTON: 1
JOB_TIMEOUT: 60
TEST_PHASE_TIMEOUT: 60
TEST_PHASE_TIMEOUT_MINUTES: 60
a618-traces:
extends:
@@ -265,7 +265,7 @@ a630_vk:
parallel: 2
variables:
DEQP_SUITE: freedreno-a630-vk-full
TEST_PHASE_TIMEOUT: 180
TEST_PHASE_TIMEOUT_MINUTES: 180
a630_vk_asan:
extends:
@@ -298,7 +298,7 @@ a630_piglit_full:
variables:
HWCI_START_WESTON: 1
DEQP_SUITE: freedreno-a630-piglit-full
TEST_PHASE_TIMEOUT: 60
TEST_PHASE_TIMEOUT_MINUTES: 60
a630-traces:
extends: