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iris: Add read-only domain for VF cache.

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This will allow us to order writes and reads of vertex and index
buffers by using the same cache tracking infrastructure introduced
previously for render and depth buffers.  The ultimate goal is to
remove the somewhat heavy-handed history flush mechanism currently
used for buffer objects, and use a single cache tracking mechanism
across the whole driver.

v2: Use C99 designated initializers (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12691>
This commit is contained in:
Francisco Jerez
2020-05-29 17:21:28 -07:00
committed by Marge Bot
parent c679dbe09c
commit ff601897fb
3 changed files with 13 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/iris/iris_bufmgr.h
+4 -1
View File
@@ -107,6 +107,8 @@ enum iris_domain {
IRIS_DOMAIN_DEPTH_WRITE,
/** Any other read-write cache. */
IRIS_DOMAIN_OTHER_WRITE,
/** Vertex cache. */
IRIS_DOMAIN_VF_READ,
/** Any other read-only cache. */
IRIS_DOMAIN_OTHER_READ,
/** Number of caching domains. */
@@ -121,7 +123,8 @@ enum iris_domain {
static inline bool
iris_domain_is_read_only(enum iris_domain access)
{
return access == IRIS_DOMAIN_OTHER_READ;
return access == IRIS_DOMAIN_OTHER_READ ||
access == IRIS_DOMAIN_VF_READ;
}
enum iris_mmap_mode {
src/gallium/drivers/iris/iris_pipe_control.c
+3 -1
View File
@@ -191,12 +191,14 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
[IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD,
};
const uint32_t invalidate_bits[NUM_IRIS_DOMAINS] = {
[IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
[IRIS_DOMAIN_DEPTH_WRITE] = PIPE_CONTROL_DEPTH_CACHE_FLUSH,
[IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE,
[IRIS_DOMAIN_OTHER_READ] = (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE),
};
@@ -231,7 +233,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
* in order to handle any WaR dependencies.
*/
if (!iris_domain_is_read_only(access)) {
for (unsigned i = IRIS_DOMAIN_OTHER_READ; i < NUM_IRIS_DOMAINS; i++) {
for (unsigned i = IRIS_DOMAIN_VF_READ; i < NUM_IRIS_DOMAINS; i++) {
assert(iris_domain_is_read_only(i));
const uint64_t seqno = READ_ONCE(bo->last_seqnos[i]);
src/gallium/drivers/iris/iris_state.c
+6 -1
View File
@@ -7366,8 +7366,10 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_WRITE);
if ((flags & (PIPE_CONTROL_CACHE_FLUSH_BITS |
PIPE_CONTROL_STALL_AT_SCOREBOARD)))
PIPE_CONTROL_STALL_AT_SCOREBOARD))) {
iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_VF_READ);
iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_READ);
}
}
if ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH))
@@ -7379,6 +7381,9 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
if ((flags & PIPE_CONTROL_FLUSH_ENABLE))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_WRITE);
if ((flags & PIPE_CONTROL_VF_CACHE_INVALIDATE))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_VF_READ);
if ((flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE) &&
(flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE))
iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_READ);