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lima/gpir: Fix 64-bit shift in scheduler spilling

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There are 64 physical registers so the shift must be 64 bits.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
This commit is contained in:
Connor Abbott
2019-09-19 00:47:28 +07:00
parent ef38a659fb
commit fed5b605f0
1 changed files with 2 additions and 2 deletions
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src/gallium/drivers/lima/ir/gp/scheduler.c
+2 -2
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@@ -861,12 +861,12 @@ static uint64_t get_available_regs(sched_ctx *ctx, gpir_node *node,
if (instr->reg0_use_count == 0)
use_available = ~0ull;
else if (!instr->reg0_is_attr)
use_available = 0xf << (4 * instr->reg0_index);
use_available = 0xfull << (4 * instr->reg0_index);
if (instr->reg1_use_count == 0)
use_available = ~0ull;
else
use_available |= 0xf << (4 * instr->reg1_index);
use_available |= 0xfull << (4 * instr->reg1_index);
available &= use_available;
}