brw: Drop FB_WRITE_LOGICAL_SRC_DST_DEPTH source

This was used for legacy depth passthrough on older hardware.  Gfx9+
doesn't actually have dst depth as part of the message, which is the
only hardware brw supports these days.

It sure looks like we were setting it though...

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>

src/intel/compiler/brw_compile_fs.cpp

@@ -27,14 +27,10 @@ brw_emit_single_fb_write(fs_visitor &s, const brw_builder &bld,
    assert(s.stage == MESA_SHADER_FRAGMENT);
    struct brw_wm_prog_data *prog_data = brw_wm_prog_data(s.prog_data);
 
-   /* Hand over gl_FragDepth or the payload depth. */
-   const brw_reg dst_depth = brw_fetch_payload_reg(bld, s.fs_payload().dest_depth_reg);
-
    brw_reg sources[FB_WRITE_LOGICAL_NUM_SRCS];
    sources[FB_WRITE_LOGICAL_SRC_COLOR0]     = color0;
    sources[FB_WRITE_LOGICAL_SRC_COLOR1]     = color1;
    sources[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA] = src0_alpha;
-   sources[FB_WRITE_LOGICAL_SRC_DST_DEPTH]  = dst_depth;
    sources[FB_WRITE_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(components);
    sources[FB_WRITE_LOGICAL_SRC_NULL_RT]    = brw_imm_ud(null_rt);
 

src/intel/compiler/brw_eu_defines.h

@@ -564,7 +564,6 @@ enum fb_write_logical_srcs {
    FB_WRITE_LOGICAL_SRC_COLOR1,      /* for dual source blend messages */
    FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
    FB_WRITE_LOGICAL_SRC_SRC_DEPTH,   /* gl_FragDepth */
-   FB_WRITE_LOGICAL_SRC_DST_DEPTH,   /* GFX4-5: passthrough from thread */
    FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
    FB_WRITE_LOGICAL_SRC_OMASK,       /* Sample Mask (gl_SampleMask) */
    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */

src/intel/compiler/brw_fs.h

@@ -100,7 +100,6 @@ struct fs_thread_payload : public thread_payload {
    uint8_t source_depth_reg[2];
    uint8_t source_w_reg[2];
    uint8_t aa_dest_stencil_reg[2];
-   uint8_t dest_depth_reg[2];
    uint8_t sample_pos_reg[2];
    uint8_t sample_mask_in_reg[2];
    uint8_t barycentric_coord_reg[INTEL_BARYCENTRIC_MODE_COUNT][2];

src/intel/compiler/brw_fs_thread_payload.cpp

@@ -338,7 +338,6 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v,
     source_depth_reg(),
     source_w_reg(),
     aa_dest_stencil_reg(),
-    dest_depth_reg(),
     sample_pos_reg(),
     sample_mask_in_reg(),
     barycentric_coord_reg(),

src/intel/compiler/brw_lower_logical_sends.cpp

@@ -292,7 +292,6 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
    const brw_reg color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1];
    const brw_reg src0_alpha = inst->src[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA];
    const brw_reg src_depth = inst->src[FB_WRITE_LOGICAL_SRC_SRC_DEPTH];
-   const brw_reg dst_depth = inst->src[FB_WRITE_LOGICAL_SRC_DST_DEPTH];
    const brw_reg src_stencil = inst->src[FB_WRITE_LOGICAL_SRC_SRC_STENCIL];
    brw_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK];
    const unsigned components =
@@ -431,20 +430,9 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
       length++;
    }
 
-   if (dst_depth.file != BAD_FILE) {
-      sources[length] = dst_depth;
-      length++;
-   }
-
    if (src_stencil.file != BAD_FILE) {
       assert(bld.dispatch_width() == 8 * reg_unit(devinfo));
 
-      /* XXX: src_stencil is only available on gfx9+. dst_depth is never
-       * available on gfx9+. As such it's impossible to have both enabled at the
-       * same time and therefore length cannot overrun the array.
-       */
-      assert(length < 15 * reg_unit(devinfo));
-
       sources[length] = bld.vgrf(BRW_TYPE_UD);
       bld.exec_all().annotate("FB write OS")
          .MOV(retype(sources[length], BRW_TYPE_UB),