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r600g: set correct tiling flags in depth info

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The kernel currently overwrites the flags, but if we stopped doing that,
this would break badly.
This commit is contained in:
Marek Olšák
2011-10-25 01:28:39 +02:00
parent 5c44c1348e
commit faa16dc456
2 changed files with 13 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/r600/evergreen_state.c
+7 -5
View File
@@ -1460,17 +1460,19 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
unsigned level, first_layer;
unsigned pitch, slice, format;
unsigned offset;
unsigned level, first_layer, pitch, slice, format, offset, array_mode;
if (state->zsbuf == NULL)
return;
surf = (struct r600_surface *)state->zsbuf;
level = surf->base.u.tex.level;
rtex = (struct r600_resource_texture*)surf->base.texture;
level = surf->base.u.tex.level;
/* XXX remove this once tiling is properly supported */
array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
V_028C70_ARRAY_1D_TILED_THIN1;
first_layer = surf->base.u.tex.first_layer;
offset = r600_texture_get_offset(rtex, level, first_layer);
pitch = rtex->pitch_in_blocks[level] / 8 - 1;
@@ -1499,7 +1501,7 @@ static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state
}
r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
S_028040_ARRAY_MODE(array_mode) | S_028040_FORMAT(format),
0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
S_028058_PITCH_TILE_MAX(pitch),
src/gallium/drivers/r600/r600_state.c
+6 -4
View File
@@ -1550,9 +1550,7 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
{
struct r600_resource_texture *rtex;
struct r600_surface *surf;
unsigned level;
unsigned pitch, slice, format;
unsigned offset;
unsigned level, pitch, slice, format, offset, array_mode;
if (state->zsbuf == NULL)
return;
@@ -1562,6 +1560,10 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
surf = (struct r600_surface *)state->zsbuf;
rtex = (struct r600_resource_texture*)state->zsbuf->texture;
/* XXX remove this once tiling is properly supported */
array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
V_0280A0_ARRAY_1D_TILED_THIN1;
/* XXX quite sure for dx10+ hw don't need any offset hacks */
offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
level, state->zsbuf->u.tex.first_layer);
@@ -1576,7 +1578,7 @@ static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
0xFFFFFFFF, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
(surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL, 0);