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radv: track more CB related context registers on < GFX12

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The tracked registers mechanism isn't used yet on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31659>
This commit is contained in:
Samuel Pitoiset
2025-08-05 13:52:45 +02:00
committed by Marge Bot
parent 6a170c5de1
commit fa677ca0c3
2 changed files with 31 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+21 -13
View File
@@ -426,8 +426,10 @@ radv_reset_tracked_regs(struct radv_cmd_buffer *cmd_buffer)
memset(tracked_regs->reg_value, 0, RADV_NUM_ALL_TRACKED_REGS * sizeof(uint32_t));
BITSET_ZERO(tracked_regs->reg_saved_mask);
/* 0xffffffff is an impossible value for SPI_PS_INPUT_CNTL_n registers */
/* 0xffffffff is an impossible value for these registers */
memset(tracked_regs->spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
memset(tracked_regs->cb_blend_control, 0xff, sizeof(uint32_t) * MAX_RTS);
memset(tracked_regs->sx_mrt_blend_opt, 0xff, sizeof(uint32_t) * MAX_RTS);
}
static void
@@ -3572,9 +3574,11 @@ radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer)
radeon_begin(cmd_buffer->cs);
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(R_028858_CB_COLOR_CONTROL, cb_color_control);
radeon_opt_set_context_reg(cmd_buffer, R_028858_CB_COLOR_CONTROL, RADV_TRACKED_CB_COLOR_CONTROL,
cb_color_control);
} else {
radeon_set_context_reg(R_028808_CB_COLOR_CONTROL, cb_color_control);
radeon_opt_set_context_reg(cmd_buffer, R_028808_CB_COLOR_CONTROL, RADV_TRACKED_CB_COLOR_CONTROL,
cb_color_control);
}
radeon_end();
}
@@ -3600,9 +3604,9 @@ radv_emit_color_write(struct radv_cmd_buffer *cmd_buffer)
radeon_begin(cmd_buffer->cs);
if (pdev->info.gfx_level >= GFX12) {
radeon_set_context_reg(R_028850_CB_TARGET_MASK, cb_target_mask);
radeon_opt_set_context_reg(cmd_buffer, R_028850_CB_TARGET_MASK, RADV_TRACKED_CB_TARGET_MASK, cb_target_mask);
} else {
radeon_set_context_reg(R_028238_CB_TARGET_MASK, cb_target_mask);
radeon_opt_set_context_reg(cmd_buffer, R_028238_CB_TARGET_MASK, RADV_TRACKED_CB_TARGET_MASK, cb_target_mask);
}
radeon_end();
}
@@ -5312,12 +5316,12 @@ radv_emit_color_blend(struct radv_cmd_buffer *cmd_buffer)
}
radeon_begin(cmd_buffer->cs);
radeon_set_context_reg_seq(R_028780_CB_BLEND0_CONTROL, MAX_RTS);
radeon_emit_array(cb_blend_control, MAX_RTS);
radeon_opt_set_context_regn(cmd_buffer, R_028780_CB_BLEND0_CONTROL, cb_blend_control,
cmd_buffer->tracked_regs.cb_blend_control, MAX_RTS);
if (pdev->info.has_rbplus) {
radeon_set_context_reg_seq(R_028760_SX_MRT0_BLEND_OPT, MAX_RTS);
radeon_emit_array(sx_mrt_blend_opt, MAX_RTS);
radeon_opt_set_context_regn(cmd_buffer, R_028760_SX_MRT0_BLEND_OPT, sx_mrt_blend_opt,
cmd_buffer->tracked_regs.sx_mrt_blend_opt, MAX_RTS);
}
radeon_end();
}
@@ -9058,6 +9062,10 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
memcpy(primary->tracked_regs.spi_ps_input_cntl, secondary->tracked_regs.spi_ps_input_cntl,
sizeof(primary->tracked_regs.spi_ps_input_cntl));
memcpy(primary->tracked_regs.cb_blend_control, secondary->tracked_regs.cb_blend_control,
sizeof(primary->tracked_regs.cb_blend_control));
memcpy(primary->tracked_regs.sx_mrt_blend_opt, secondary->tracked_regs.sx_mrt_blend_opt,
sizeof(primary->tracked_regs.sx_mrt_blend_opt));
}
/* After executing commands from secondary buffers we have to dirty
@@ -10832,10 +10840,10 @@ radv_emit_fragment_output_state(struct radv_cmd_buffer *cmd_buffer)
radeon_end();
} else {
radeon_begin(cmd_buffer->cs);
radeon_set_context_reg(R_02823C_CB_SHADER_MASK, cmd_buffer->state.cb_shader_mask);
radeon_set_context_reg_seq(R_028710_SPI_SHADER_Z_FORMAT, 2);
radeon_emit(cmd_buffer->state.spi_shader_z_format);
radeon_emit(col_format_compacted); /* SPI_SHADER_COL_FORMAT */
radeon_opt_set_context_reg(cmd_buffer, R_02823C_CB_SHADER_MASK, RADV_TRACKED_CB_SHADER_MASK,
cmd_buffer->state.cb_shader_mask);
radeon_opt_set_context_reg2(cmd_buffer, R_028710_SPI_SHADER_Z_FORMAT, RADV_TRACKED_SPI_SHADER_Z_FORMAT,
cmd_buffer->state.spi_shader_z_format, col_format_compacted);
radeon_end();
}
src/amd/vulkan/radv_cmd_buffer.h
+10 -1
View File
@@ -301,7 +301,6 @@ enum radv_tracked_reg {
RADV_TRACKED_SPI_SHADER_IDX_FORMAT,
RADV_TRACKED_SPI_SHADER_POS_FORMAT,
RADV_TRACKED_SPI_SHADER_Z_FORMAT,
RADV_TRACKED_SPI_VS_OUT_CONFIG,
/* 3 consecutive registers */
@@ -352,6 +351,14 @@ enum radv_tracked_reg {
RADV_TRACKED_DB_RENDER_OVERRIDE, /* GFX12+ */
/* 2 consecutive registers */
RADV_TRACKED_SPI_SHADER_Z_FORMAT,
RADV_TRACKED_SPI_SHADER_COL_FORMAT,
RADV_TRACKED_CB_TARGET_MASK,
RADV_TRACKED_CB_COLOR_CONTROL,
RADV_TRACKED_CB_SHADER_MASK,
RADV_NUM_ALL_TRACKED_REGS,
};
@@ -359,6 +366,8 @@ struct radv_tracked_regs {
BITSET_DECLARE(reg_saved_mask, RADV_NUM_ALL_TRACKED_REGS);
uint32_t reg_value[RADV_NUM_ALL_TRACKED_REGS];
uint32_t spi_ps_input_cntl[32];
uint32_t cb_blend_control[MAX_RTS];
uint32_t sx_mrt_blend_opt[MAX_RTS];
};
struct radv_cmd_state {