radeonsi: fast exit si_emit_derived_tess_state early
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@@ -336,6 +336,7 @@ struct si_context {
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struct si_shader_selector *last_tcs;
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int last_num_tcs_input_cp;
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int last_tes_sh_base;
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unsigned last_num_patches;
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/* Debug state. */
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bool is_debug;
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@@ -108,6 +108,19 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
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unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
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unsigned offchip_layout, hardware_lds_size, ls_hs_config;
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if (sctx->last_ls == ls->current &&
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sctx->last_tcs == tcs &&
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sctx->last_tes_sh_base == tes_sh_base &&
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sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
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*num_patches = sctx->last_num_patches;
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return;
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}
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sctx->last_ls = ls->current;
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sctx->last_tcs = tcs;
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sctx->last_tes_sh_base = tes_sh_base;
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sctx->last_num_tcs_input_cp = num_tcs_input_cp;
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/* This calculates how shader inputs and outputs among VS, TCS, and TES
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* are laid out in LDS. */
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num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
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@@ -153,6 +166,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
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* specific value is taken from the proprietary driver.
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*/
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*num_patches = MIN2(*num_patches, 40);
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sctx->last_num_patches = *num_patches;
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output_patch0_offset = input_patch_size * *num_patches;
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perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
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@@ -168,17 +182,6 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
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ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
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}
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if (sctx->last_ls == ls->current &&
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sctx->last_tcs == tcs &&
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sctx->last_tes_sh_base == tes_sh_base &&
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sctx->last_num_tcs_input_cp == num_tcs_input_cp)
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return;
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sctx->last_ls = ls->current;
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sctx->last_tcs = tcs;
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sctx->last_tes_sh_base = tes_sh_base;
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sctx->last_num_tcs_input_cp = num_tcs_input_cp;
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/* Due to a hw bug, RSRC2_LS must be written twice with another
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* LS register written in between. */
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if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
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