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nvc0: preliminary tess support

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Uncomment the various functionality that was already there and add in
obvious missing bits that parallel vp/gp/fp functionality.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin
2014-07-12 15:40:14 -04:00
parent 65d84daf29
commit f97c14f9e4
10 changed files with 86 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+2 -2
View File
@@ -1153,8 +1153,8 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
switch (info->type) {
PROG_TYPE_CASE(VERTEX, VERTEX);
// PROG_TYPE_CASE(HULL, TESSELLATION_CONTROL);
// PROG_TYPE_CASE(DOMAIN, TESSELLATION_EVAL);
PROG_TYPE_CASE(TESS_CTRL, TESSELLATION_CONTROL);
PROG_TYPE_CASE(TESS_EVAL, TESSELLATION_EVAL);
PROG_TYPE_CASE(GEOMETRY, GEOMETRY);
PROG_TYPE_CASE(FRAGMENT, FRAGMENT);
PROG_TYPE_CASE(COMPUTE, COMPUTE);
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
-5
View File
@@ -74,11 +74,6 @@ struct nv50_ir_varying
#define NV50_SEMANTIC_TESSCOORD (TGSI_SEMANTIC_COUNT + 8)
#define NV50_SEMANTIC_COUNT (TGSI_SEMANTIC_COUNT + 10)
#define NV50_TESS_PART_FRACT_ODD 0
#define NV50_TESS_PART_FRACT_EVEN 1
#define NV50_TESS_PART_POW2 2
#define NV50_TESS_PART_INTEGER 3
#define NV50_PRIM_PATCHES PIPE_PRIM_MAX
struct nv50_ir_prog_symbol
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+2
View File
@@ -372,6 +372,8 @@ static nv50_ir::SVSemantic translateSysVal(uint sysval)
case TGSI_SEMANTIC_SAMPLEPOS: return nv50_ir::SV_SAMPLE_POS;
case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
case TGSI_SEMANTIC_TESSCOORD: return nv50_ir::SV_TESS_COORD;
case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
default:
assert(0);
return nv50_ir::SV_CLOCK;
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+2 -2
View File
@@ -195,8 +195,8 @@ nvc0_shader_stage(unsigned pipe)
{
switch (pipe) {
case PIPE_SHADER_VERTEX: return 0;
/* case PIPE_SHADER_TESSELLATION_CONTROL: return 1; */
/* case PIPE_SHADER_TESSELLATION_EVALUATION: return 2; */
case PIPE_SHADER_TESS_CTRL: return 1;
case PIPE_SHADER_TESS_EVAL: return 2;
case PIPE_SHADER_GEOMETRY: return 3;
case PIPE_SHADER_FRAGMENT: return 4;
case PIPE_SHADER_COMPUTE: return 5;
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+10 -19
View File
@@ -34,7 +34,8 @@ static uint32_t
nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
{
switch (sn) {
case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
case TGSI_SEMANTIC_PRIMID: return 0x060;
case TGSI_SEMANTIC_LAYER: return 0x064;
case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
@@ -48,7 +49,7 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
case TGSI_SEMANTIC_PCOORD: return 0x2e0;
case NV50_SEMANTIC_TESSCOORD: return 0x2f0;
case TGSI_SEMANTIC_TESSCOORD: return 0x2f0;
case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
@@ -63,7 +64,8 @@ static uint32_t
nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
{
switch (sn) {
case NV50_SEMANTIC_TESSFACTOR: return 0x000 + si * 0x4;
case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
case TGSI_SEMANTIC_TESSINNER: return 0x010 + si * 0x4;
case TGSI_SEMANTIC_PRIMID: return 0x060;
case TGSI_SEMANTIC_LAYER: return 0x064;
case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
@@ -277,7 +279,6 @@ nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
return nvc0_vtgp_gen_header(vp, info);
}
#if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
static void
nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
{
@@ -305,14 +306,13 @@ nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
switch (info->prop.tp.partitioning) {
case PIPE_TESS_PART_INTEGER:
case PIPE_TESS_PART_POW2:
case PIPE_TESS_SPACING_EQUAL:
tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
break;
case PIPE_TESS_PART_FRACT_ODD:
case PIPE_TESS_SPACING_FRACTIONAL_ODD:
tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
break;
case PIPE_TESS_PART_FRACT_EVEN:
case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
break;
default:
@@ -320,9 +320,7 @@ nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
break;
}
}
#endif
#ifdef PIPE_SHADER_HULL
static int
nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
{
@@ -346,9 +344,7 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
return 0;
}
#endif
#ifdef PIPE_SHADER_DOMAIN
static int
nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
{
@@ -365,7 +361,6 @@ nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
return 0;
}
#endif
static int
nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
@@ -598,16 +593,12 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
case PIPE_SHADER_VERTEX:
ret = nvc0_vp_gen_header(prog, info);
break;
#ifdef PIPE_SHADER_HULL
case PIPE_SHADER_HULL:
case PIPE_SHADER_TESS_CTRL:
ret = nvc0_tcp_gen_header(prog, info);
break;
#endif
#ifdef PIPE_SHADER_DOMAIN
case PIPE_SHADER_DOMAIN:
case PIPE_SHADER_TESS_EVAL:
ret = nvc0_tep_gen_header(prog, info);
break;
#endif
case PIPE_SHADER_GEOMETRY:
ret = nvc0_gp_gen_header(prog, info);
break;
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+2 -4
View File
@@ -228,10 +228,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
switch (shader) {
case PIPE_SHADER_VERTEX:
/*
case PIPE_SHADER_TESSELLATION_CONTROL:
case PIPE_SHADER_TESSELLATION_EVALUATION:
*/
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_FRAGMENT:
break;
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+52
View File
@@ -508,6 +508,14 @@ nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
assert(start == 0);
nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
break;
case PIPE_SHADER_TESS_CTRL:
assert(start == 0);
nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
break;
case PIPE_SHADER_TESS_EVAL:
assert(start == 0);
nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
break;
case PIPE_SHADER_GEOMETRY:
assert(start == 0);
nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
@@ -633,6 +641,12 @@ nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
case PIPE_SHADER_VERTEX:
nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
break;
case PIPE_SHADER_TESS_CTRL:
nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
break;
case PIPE_SHADER_TESS_EVAL:
nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
break;
case PIPE_SHADER_GEOMETRY:
nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
break;
@@ -733,6 +747,38 @@ nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
nvc0->dirty |= NVC0_NEW_GMTYPROG;
}
static void *
nvc0_tcp_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
}
static void
nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
nvc0->tctlprog = hwcso;
nvc0->dirty |= NVC0_NEW_TCTLPROG;
}
static void *
nvc0_tep_state_create(struct pipe_context *pipe,
const struct pipe_shader_state *cso)
{
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
}
static void
nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
{
struct nvc0_context *nvc0 = nvc0_context(pipe);
nvc0->tevlprog = hwcso;
nvc0->dirty |= NVC0_NEW_TEVLPROG;
}
static void *
nvc0_cp_state_create(struct pipe_context *pipe,
const struct pipe_compute_state *cso)
@@ -1220,12 +1266,18 @@ nvc0_init_state_functions(struct nvc0_context *nvc0)
pipe->create_vs_state = nvc0_vp_state_create;
pipe->create_fs_state = nvc0_fp_state_create;
pipe->create_gs_state = nvc0_gp_state_create;
pipe->create_tcs_state = nvc0_tcp_state_create;
pipe->create_tes_state = nvc0_tep_state_create;
pipe->bind_vs_state = nvc0_vp_state_bind;
pipe->bind_fs_state = nvc0_fp_state_bind;
pipe->bind_gs_state = nvc0_gp_state_bind;
pipe->bind_tcs_state = nvc0_tcp_state_bind;
pipe->bind_tes_state = nvc0_tep_state_bind;
pipe->delete_vs_state = nvc0_sp_state_delete;
pipe->delete_fs_state = nvc0_sp_state_delete;
pipe->delete_gs_state = nvc0_sp_state_delete;
pipe->delete_tcs_state = nvc0_sp_state_delete;
pipe->delete_tes_state = nvc0_sp_state_delete;
pipe->create_compute_state = nvc0_cp_state_create;
pipe->bind_compute_state = nvc0_cp_state_bind;
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+14 -18
View File
@@ -356,16 +356,14 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
void nvc0_validate_textures(struct nvc0_context *nvc0)
{
bool need_flush;
bool need_flush = false;
int i;
if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) {
need_flush = nve4_validate_tic(nvc0, 0);
need_flush |= nve4_validate_tic(nvc0, 3);
need_flush |= nve4_validate_tic(nvc0, 4);
} else {
need_flush = nvc0_validate_tic(nvc0, 0);
need_flush |= nvc0_validate_tic(nvc0, 3);
need_flush |= nvc0_validate_tic(nvc0, 4);
for (i = 0; i < 5; i++) {
if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
need_flush |= nve4_validate_tic(nvc0, i);
else
need_flush |= nvc0_validate_tic(nvc0, i);
}
if (need_flush) {
@@ -466,16 +464,14 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s)
void nvc0_validate_samplers(struct nvc0_context *nvc0)
{
bool need_flush;
bool need_flush = false;
int i;
if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) {
need_flush = nve4_validate_tsc(nvc0, 0);
need_flush |= nve4_validate_tsc(nvc0, 3);
need_flush |= nve4_validate_tsc(nvc0, 4);
} else {
need_flush = nvc0_validate_tsc(nvc0, 0);
need_flush |= nvc0_validate_tsc(nvc0, 3);
need_flush |= nvc0_validate_tsc(nvc0, 4);
for (i = 0; i < 5; i++) {
if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
need_flush |= nve4_validate_tsc(nvc0, i);
else
need_flush |= nvc0_validate_tsc(nvc0, i);
}
if (need_flush) {
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+1 -2
View File
@@ -547,8 +547,7 @@ nvc0_prim_gl(unsigned prim)
NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
/*
NVC0_PRIM_GL_CASE(PATCHES); */
NVC0_PRIM_GL_CASE(PATCHES);
default:
return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
}
src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
+1 -2
View File
@@ -427,8 +427,7 @@ nvc0_prim_gl(unsigned prim)
NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
/*
NVC0_PRIM_GL_CASE(PATCHES); */
NVC0_PRIM_GL_CASE(PATCHES);
default:
return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
}