intel/brw: Rename and move thread_payload types to own header

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32536>

src/intel/compiler/brw_compile_bs.cpp

@@ -36,7 +36,7 @@ run_bs(fs_visitor &s, bool allow_spilling)
 {
    assert(s.stage >= MESA_SHADER_RAYGEN && s.stage <= MESA_SHADER_CALLABLE);
 
-   s.payload_ = new bs_thread_payload(s);
+   s.payload_ = new brw_bs_thread_payload(s);
 
    brw_from_nir(&s);
 

src/intel/compiler/brw_compile_cs.cpp

@@ -64,7 +64,7 @@ run_cs(fs_visitor &s, bool allow_spilling)
    assert(gl_shader_stage_is_compute(s.stage));
    const brw_builder bld = brw_builder(&s).at_end();
 
-   s.payload_ = new cs_thread_payload(s);
+   s.payload_ = new brw_cs_thread_payload(s);
 
    if (s.devinfo->platform == INTEL_PLATFORM_HSW && s.prog_data->total_shared > 0) {
       /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */

src/intel/compiler/brw_compile_fs.cpp

@@ -187,7 +187,7 @@ brw_emit_interpolation_setup(fs_visitor &s)
 
    const struct brw_wm_prog_key *wm_key = (brw_wm_prog_key*) s.key;
    struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data);
-   fs_thread_payload &payload = s.fs_payload();
+   brw_fs_thread_payload &payload = s.fs_payload();
 
    brw_reg int_sample_offset_x, int_sample_offset_y; /* Used on Gen12HP+ */
    brw_reg int_sample_offset_xy; /* Used on Gen8+ */
@@ -1459,7 +1459,7 @@ run_fs(fs_visitor &s, bool allow_spilling, bool do_rep_send)
 
    assert(s.stage == MESA_SHADER_FRAGMENT);
 
-   s.payload_ = new fs_thread_payload(s, s.source_depth_to_render_target);
+   s.payload_ = new brw_fs_thread_payload(s, s.source_depth_to_render_target);
 
    if (nir->info.ray_queries > 0)
       s.limit_dispatch_width(16, "SIMD32 not supported with ray queries.\n");

src/intel/compiler/brw_compile_gs.cpp

@@ -88,7 +88,7 @@ run_gs(fs_visitor &s)
 {
    assert(s.stage == MESA_SHADER_GEOMETRY);
 
-   s.payload_ = new gs_thread_payload(s);
+   s.payload_ = new brw_gs_thread_payload(s);
 
    const brw_builder bld = brw_builder(&s).at_end();
 

src/intel/compiler/brw_compile_mesh.cpp

@@ -319,7 +319,7 @@ run_task_mesh(fs_visitor &s, bool allow_spilling)
    assert(s.stage == MESA_SHADER_TASK ||
           s.stage == MESA_SHADER_MESH);
 
-   s.payload_ = new task_mesh_thread_payload(s);
+   s.payload_ = new brw_task_mesh_thread_payload(s);
 
    brw_from_nir(&s);
 

src/intel/compiler/brw_compile_tcs.cpp

@@ -136,7 +136,7 @@ run_tcs(fs_visitor &s)
    assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH ||
           vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH);
 
-   s.payload_ = new tcs_thread_payload(s);
+   s.payload_ = new brw_tcs_thread_payload(s);
 
    /* Initialize gl_InvocationID */
    brw_set_tcs_invocation_id(s);

src/intel/compiler/brw_compile_tes.cpp

@@ -32,7 +32,7 @@ run_tes(fs_visitor &s)
 {
    assert(s.stage == MESA_SHADER_TESS_EVAL);
 
-   s.payload_ = new tes_thread_payload(s);
+   s.payload_ = new brw_tes_thread_payload(s);
 
    brw_from_nir(&s);
 

src/intel/compiler/brw_compile_vs.cpp

@@ -33,7 +33,7 @@ run_vs(fs_visitor &s)
 {
    assert(s.stage == MESA_SHADER_VERTEX);
 
-   s.payload_ = new vs_thread_payload(s);
+   s.payload_ = new brw_vs_thread_payload(s);
 
    brw_from_nir(&s);
 

src/intel/compiler/brw_from_nir.cpp

@@ -2163,7 +2163,7 @@ emit_pixel_interpolater_alu_at_offset(const brw_builder &bld,
    const intel_device_info *devinfo = shader->devinfo;
    assert(devinfo->ver >= 11);
 
-   const fs_thread_payload &payload = shader->fs_payload();
+   const brw_fs_thread_payload &payload = shader->fs_payload();
    const struct brw_wm_prog_data *wm_prog_data =
       brw_wm_prog_data(shader->prog_data);
 
@@ -2293,7 +2293,7 @@ emit_pixel_interpolater_alu_at_sample(const brw_builder &bld,
                                       const brw_reg &idx,
                                       glsl_interp_mode interpolation)
 {
-   const fs_thread_payload &payload = bld.shader->fs_payload();
+   const brw_fs_thread_payload &payload = bld.shader->fs_payload();
    const struct brw_wm_prog_data *wm_prog_data =
       brw_wm_prog_data(bld.shader->prog_data);
    const brw_builder ubld = bld.exec_all().group(16, 0);
@@ -4635,7 +4635,7 @@ brw_from_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
       break;
 
    case nir_intrinsic_load_inline_data_intel: {
-      const cs_thread_payload &payload = s.cs_payload();
+      const brw_cs_thread_payload &payload = s.cs_payload();
       unsigned inline_stride = brw_type_size_bytes(dest.type);
       for (unsigned c = 0; c < instr->def.num_components; c++) {
          xbld.MOV(offset(dest, xbld, c),
@@ -4773,7 +4773,7 @@ brw_from_nir_emit_bs_intrinsic(nir_to_brw_state &ntb,
    fs_visitor &s = ntb.s;
 
    assert(brw_shader_stage_is_bindless(s.stage));
-   const bs_thread_payload &payload = s.bs_payload();
+   const brw_bs_thread_payload &payload = s.bs_payload();
 
    brw_reg dest;
    if (nir_intrinsic_infos[instr->intrinsic].has_dest)
@@ -5621,7 +5621,7 @@ brw_from_nir_emit_task_mesh_intrinsic(nir_to_brw_state &ntb, const brw_builder &
    fs_visitor &s = ntb.s;
 
    assert(s.stage == MESA_SHADER_MESH || s.stage == MESA_SHADER_TASK);
-   const task_mesh_thread_payload &payload = s.task_mesh_payload();
+   const brw_task_mesh_thread_payload &payload = s.task_mesh_payload();
 
    brw_reg dest;
    if (nir_intrinsic_infos[instr->intrinsic].has_dest)
@@ -5668,7 +5668,7 @@ brw_from_nir_emit_task_intrinsic(nir_to_brw_state &ntb,
    fs_visitor &s = ntb.s;
 
    assert(s.stage == MESA_SHADER_TASK);
-   const task_mesh_thread_payload &payload = s.task_mesh_payload();
+   const brw_task_mesh_thread_payload &payload = s.task_mesh_payload();
 
    switch (instr->intrinsic) {
    case nir_intrinsic_store_output:
@@ -5695,7 +5695,7 @@ brw_from_nir_emit_mesh_intrinsic(nir_to_brw_state &ntb,
    fs_visitor &s = ntb.s;
 
    assert(s.stage == MESA_SHADER_MESH);
-   const task_mesh_thread_payload &payload = s.task_mesh_payload();
+   const brw_task_mesh_thread_payload &payload = s.task_mesh_payload();
 
    switch (instr->intrinsic) {
    case nir_intrinsic_store_per_primitive_output:

src/intel/compiler/brw_fs.h

@@ -33,13 +33,10 @@
 #include "brw_inst.h"
 #include "compiler/nir/nir.h"
 #include "brw_analysis.h"
-
-struct fs_visitor;
+#include "brw_thread_payload.h"
 
 #define UBO_START ((1 << 16) - 4)
 
-class brw_builder;
-
 struct brw_shader_stats {
    const char *scheduler_mode;
    unsigned promoted_constants;
@@ -49,103 +46,6 @@ struct brw_shader_stats {
    unsigned non_ssa_registers_after_nir;
 };
 
-/** Register numbers for thread payload fields. */
-struct thread_payload {
-   /** The number of thread payload registers the hardware will supply. */
-   uint8_t num_regs;
-
-   virtual ~thread_payload() = default;
-
-protected:
-   thread_payload() : num_regs() {}
-};
-
-struct vs_thread_payload : public thread_payload {
-   vs_thread_payload(const fs_visitor &v);
-
-   brw_reg urb_handles;
-};
-
-struct tcs_thread_payload : public thread_payload {
-   tcs_thread_payload(const fs_visitor &v);
-
-   brw_reg patch_urb_output;
-   brw_reg primitive_id;
-   brw_reg icp_handle_start;
-};
-
-struct tes_thread_payload : public thread_payload {
-   tes_thread_payload(const fs_visitor &v);
-
-   brw_reg patch_urb_input;
-   brw_reg primitive_id;
-   brw_reg coords[3];
-   brw_reg urb_output;
-};
-
-struct gs_thread_payload : public thread_payload {
-   gs_thread_payload(fs_visitor &v);
-
-   brw_reg urb_handles;
-   brw_reg primitive_id;
-   brw_reg instance_id;
-   brw_reg icp_handle_start;
-};
-
-struct fs_thread_payload : public thread_payload {
-   fs_thread_payload(const fs_visitor &v,
-                     bool &source_depth_to_render_target);
-
-   uint8_t subspan_coord_reg[2];
-   uint8_t source_depth_reg[2];
-   uint8_t source_w_reg[2];
-   uint8_t aa_dest_stencil_reg[2];
-   uint8_t sample_pos_reg[2];
-   uint8_t sample_mask_in_reg[2];
-   uint8_t barycentric_coord_reg[INTEL_BARYCENTRIC_MODE_COUNT][2];
-
-   uint8_t depth_w_coef_reg;
-   uint8_t pc_bary_coef_reg;
-   uint8_t npc_bary_coef_reg;
-   uint8_t sample_offsets_reg;
-};
-
-struct cs_thread_payload : public thread_payload {
-   cs_thread_payload(const fs_visitor &v);
-
-   void load_subgroup_id(const brw_builder &bld, brw_reg &dest) const;
-
-   brw_reg local_invocation_id[3];
-
-   brw_reg inline_parameter;
-
-protected:
-   brw_reg subgroup_id_;
-};
-
-struct task_mesh_thread_payload : public cs_thread_payload {
-   task_mesh_thread_payload(fs_visitor &v);
-
-   brw_reg extended_parameter_0;
-   brw_reg local_index;
-
-   brw_reg urb_output;
-
-   /* URB to read Task memory inputs. Only valid for MESH stage. */
-   brw_reg task_urb_input;
-};
-
-struct bs_thread_payload : public thread_payload {
-   bs_thread_payload(const fs_visitor &v);
-
-   brw_reg inline_parameter;
-
-   brw_reg global_arg_ptr;
-   brw_reg local_arg_ptr;
-
-   void load_shader_type(const brw_builder &bld, brw_reg &dest) const;
-};
-
 enum brw_shader_phase {
    BRW_SHADER_PHASE_INITIAL = 0,
    BRW_SHADER_PHASE_AFTER_NIR,
@@ -263,56 +163,31 @@ public:
    bool failed;
    char *fail_msg;
 
-   thread_payload *payload_;
+   /* Use the vs_payload(), fs_payload(), etc. to access the right payload. */
+   brw_thread_payload *payload_;
 
-   thread_payload &payload() {
-      return *this->payload_;
+#define DEFINE_PAYLOAD_ACCESSOR(TYPE, NAME, ASSERTION)   \
+   TYPE &NAME() {                                        \
+      assert(ASSERTION);                                 \
+      return *static_cast<TYPE *>(this->payload_);       \
+   }                                                     \
+   const TYPE &NAME() const {                            \
+      assert(ASSERTION);                                 \
+      return *static_cast<const TYPE *>(this->payload_); \
    }
 
-   vs_thread_payload &vs_payload() {
-      assert(stage == MESA_SHADER_VERTEX);
-      return *static_cast<vs_thread_payload *>(this->payload_);
-   }
-
-   tcs_thread_payload &tcs_payload() {
-      assert(stage == MESA_SHADER_TESS_CTRL);
-      return *static_cast<tcs_thread_payload *>(this->payload_);
-   }
-
-   tes_thread_payload &tes_payload() {
-      assert(stage == MESA_SHADER_TESS_EVAL);
-      return *static_cast<tes_thread_payload *>(this->payload_);
-   }
-
-   gs_thread_payload &gs_payload() {
-      assert(stage == MESA_SHADER_GEOMETRY);
-      return *static_cast<gs_thread_payload *>(this->payload_);
-   }
-
-   fs_thread_payload &fs_payload() {
-      assert(stage == MESA_SHADER_FRAGMENT);
-      return *static_cast<fs_thread_payload *>(this->payload_);
-   };
-
-   const fs_thread_payload &fs_payload() const {
-      assert(stage == MESA_SHADER_FRAGMENT);
-      return *static_cast<const fs_thread_payload *>(this->payload_);
-   };
-
-   cs_thread_payload &cs_payload() {
-      assert(gl_shader_stage_uses_workgroup(stage));
-      return *static_cast<cs_thread_payload *>(this->payload_);
-   }
-
-   task_mesh_thread_payload &task_mesh_payload() {
-      assert(stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH);
-      return *static_cast<task_mesh_thread_payload *>(this->payload_);
-   }
-
-   bs_thread_payload &bs_payload() {
-      assert(stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
-      return *static_cast<bs_thread_payload *>(this->payload_);
-   }
+   DEFINE_PAYLOAD_ACCESSOR(brw_thread_payload,     payload,     true);
+   DEFINE_PAYLOAD_ACCESSOR(brw_vs_thread_payload,  vs_payload,  stage == MESA_SHADER_VERTEX);
+   DEFINE_PAYLOAD_ACCESSOR(brw_tcs_thread_payload, tcs_payload, stage == MESA_SHADER_TESS_CTRL);
+   DEFINE_PAYLOAD_ACCESSOR(brw_tes_thread_payload, tes_payload, stage == MESA_SHADER_TESS_EVAL);
+   DEFINE_PAYLOAD_ACCESSOR(brw_gs_thread_payload,  gs_payload,  stage == MESA_SHADER_GEOMETRY);
+   DEFINE_PAYLOAD_ACCESSOR(brw_fs_thread_payload,  fs_payload,  stage == MESA_SHADER_FRAGMENT);
+   DEFINE_PAYLOAD_ACCESSOR(brw_cs_thread_payload,  cs_payload,
+                           gl_shader_stage_uses_workgroup(stage));
+   DEFINE_PAYLOAD_ACCESSOR(brw_task_mesh_thread_payload, task_mesh_payload,
+                           stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH);
+   DEFINE_PAYLOAD_ACCESSOR(brw_bs_thread_payload, bs_payload,
+                           stage >= MESA_SHADER_RAYGEN && stage <= MESA_SHADER_CALLABLE);
 
    bool source_depth_to_render_target;
 

src/intel/compiler/brw_lower_logical_sends.cpp

@@ -283,7 +283,7 @@ static void
 lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
                             const struct brw_wm_prog_data *prog_data,
                             const brw_wm_prog_key *key,
-                            const fs_thread_payload &fs_payload)
+                            const brw_fs_thread_payload &fs_payload)
 {
    assert(inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
    assert(inst->src[FB_WRITE_LOGICAL_SRC_NULL_RT].file == IMM);

src/intel/compiler/brw_thread_payload.cpp

@@ -24,7 +24,7 @@
 #include "brw_fs.h"
 #include "brw_builder.h"
 
-vs_thread_payload::vs_thread_payload(const fs_visitor &v)
+brw_vs_thread_payload::brw_vs_thread_payload(const fs_visitor &v)
 {
    unsigned r = 0;
 
@@ -38,7 +38,7 @@ vs_thread_payload::vs_thread_payload(const fs_visitor &v)
    num_regs = r;
 }
 
-tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
+brw_tcs_thread_payload::brw_tcs_thread_payload(const fs_visitor &v)
 {
    struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data);
    struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(v.prog_data);
@@ -76,7 +76,7 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
    }
 }
 
-tes_thread_payload::tes_thread_payload(const fs_visitor &v)
+brw_tes_thread_payload::brw_tes_thread_payload(const fs_visitor &v)
 {
    unsigned r = 0;
 
@@ -98,7 +98,7 @@ tes_thread_payload::tes_thread_payload(const fs_visitor &v)
    num_regs = r;
 }
 
-gs_thread_payload::gs_thread_payload(fs_visitor &v)
+brw_gs_thread_payload::brw_gs_thread_payload(fs_visitor &v)
 {
    struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data);
    struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(v.prog_data);
@@ -154,7 +154,7 @@ gs_thread_payload::gs_thread_payload(fs_visitor &v)
 }
 
 static inline void
-setup_fs_payload_gfx20(fs_thread_payload &payload,
+setup_fs_payload_gfx20(brw_fs_thread_payload &payload,
                        const fs_visitor &v,
                        bool &source_depth_to_render_target)
 {
@@ -243,7 +243,7 @@ setup_fs_payload_gfx20(fs_thread_payload &payload,
 }
 
 static inline void
-setup_fs_payload_gfx9(fs_thread_payload &payload,
+setup_fs_payload_gfx9(brw_fs_thread_payload &payload,
                       const fs_visitor &v,
                       bool &source_depth_to_render_target)
 {
@@ -332,7 +332,7 @@ setup_fs_payload_gfx9(fs_thread_payload &payload,
    }
 }
 
-fs_thread_payload::fs_thread_payload(const fs_visitor &v,
+brw_fs_thread_payload::brw_fs_thread_payload(const fs_visitor &v,
                                      bool &source_depth_to_render_target)
   : subspan_coord_reg(),
     source_depth_reg(),
@@ -352,7 +352,7 @@ fs_thread_payload::fs_thread_payload(const fs_visitor &v,
       setup_fs_payload_gfx9(*this, v, source_depth_to_render_target);
 }
 
-cs_thread_payload::cs_thread_payload(const fs_visitor &v)
+brw_cs_thread_payload::brw_cs_thread_payload(const fs_visitor &v)
 {
    struct brw_cs_prog_data *prog_data = brw_cs_prog_data(v.prog_data);
 
@@ -393,7 +393,7 @@ cs_thread_payload::cs_thread_payload(const fs_visitor &v)
 }
 
 void
-cs_thread_payload::load_subgroup_id(const brw_builder &bld,
+brw_cs_thread_payload::load_subgroup_id(const brw_builder &bld,
                                     brw_reg &dest) const
 {
    auto devinfo = bld.shader->devinfo;
@@ -411,8 +411,8 @@ cs_thread_payload::load_subgroup_id(const brw_builder &bld,
    }
 }
 
-task_mesh_thread_payload::task_mesh_thread_payload(fs_visitor &v)
-   : cs_thread_payload(v)
+brw_task_mesh_thread_payload::brw_task_mesh_thread_payload(fs_visitor &v)
+   : brw_cs_thread_payload(v)
 {
    /* Task and Mesh Shader Payloads (SIMD8 and SIMD16)
     *
@@ -475,7 +475,7 @@ task_mesh_thread_payload::task_mesh_thread_payload(fs_visitor &v)
    num_regs = r;
 }
 
-bs_thread_payload::bs_thread_payload(const fs_visitor &v)
+brw_bs_thread_payload::brw_bs_thread_payload(const fs_visitor &v)
 {
    struct brw_bs_prog_data *prog_data = brw_bs_prog_data(v.prog_data);
 
@@ -498,7 +498,7 @@ bs_thread_payload::bs_thread_payload(const fs_visitor &v)
 }
 
 void
-bs_thread_payload::load_shader_type(const brw_builder &bld, brw_reg &dest) const
+brw_bs_thread_payload::load_shader_type(const brw_builder &bld, brw_reg &dest) const
 {
    brw_reg ud_dest = retype(dest, BRW_TYPE_UD);
    bld.MOV(ud_dest, retype(brw_vec1_grf(0, 3), ud_dest.type));

src/intel/compiler/brw_thread_payload.h

@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ * SPDX-License-Identifier: MIT
+ */
+
+#pragma once
+
+#include "brw_reg.h"
+
+struct fs_visitor;
+class brw_builder;
+
+struct brw_thread_payload {
+   /** The number of thread payload registers the hardware will supply. */
+   uint8_t num_regs;
+
+   virtual ~brw_thread_payload() = default;
+
+protected:
+   brw_thread_payload() : num_regs() {}
+};
+
+struct brw_vs_thread_payload : public brw_thread_payload {
+   brw_vs_thread_payload(const fs_visitor &v);
+
+   brw_reg urb_handles;
+};
+
+struct brw_tcs_thread_payload : public brw_thread_payload {
+   brw_tcs_thread_payload(const fs_visitor &v);
+
+   brw_reg patch_urb_output;
+   brw_reg primitive_id;
+   brw_reg icp_handle_start;
+};
+
+struct brw_tes_thread_payload : public brw_thread_payload {
+   brw_tes_thread_payload(const fs_visitor &v);
+
+   brw_reg patch_urb_input;
+   brw_reg primitive_id;
+   brw_reg coords[3];
+   brw_reg urb_output;
+};
+
+struct brw_gs_thread_payload : public brw_thread_payload {
+   brw_gs_thread_payload(fs_visitor &v);
+
+   brw_reg urb_handles;
+   brw_reg primitive_id;
+   brw_reg instance_id;
+   brw_reg icp_handle_start;
+};
+
+struct brw_fs_thread_payload : public brw_thread_payload {
+   brw_fs_thread_payload(const fs_visitor &v,
+                     bool &source_depth_to_render_target);
+
+   uint8_t subspan_coord_reg[2];
+   uint8_t source_depth_reg[2];
+   uint8_t source_w_reg[2];
+   uint8_t aa_dest_stencil_reg[2];
+   uint8_t sample_pos_reg[2];
+   uint8_t sample_mask_in_reg[2];
+   uint8_t barycentric_coord_reg[INTEL_BARYCENTRIC_MODE_COUNT][2];
+
+   uint8_t depth_w_coef_reg;
+   uint8_t pc_bary_coef_reg;
+   uint8_t npc_bary_coef_reg;
+   uint8_t sample_offsets_reg;
+};
+
+struct brw_cs_thread_payload : public brw_thread_payload {
+   brw_cs_thread_payload(const fs_visitor &v);
+
+   void load_subgroup_id(const brw_builder &bld, brw_reg &dest) const;
+
+   brw_reg local_invocation_id[3];
+
+   brw_reg inline_parameter;
+
+protected:
+   brw_reg subgroup_id_;
+};
+
+struct brw_task_mesh_thread_payload : public brw_cs_thread_payload {
+   brw_task_mesh_thread_payload(fs_visitor &v);
+
+   brw_reg extended_parameter_0;
+   brw_reg local_index;
+
+   brw_reg urb_output;
+
+   /* URB to read Task memory inputs. Only valid for MESH stage. */
+   brw_reg task_urb_input;
+};
+
+struct brw_bs_thread_payload : public brw_thread_payload {
+   brw_bs_thread_payload(const fs_visitor &v);
+
+   brw_reg inline_parameter;
+
+   brw_reg global_arg_ptr;
+   brw_reg local_arg_ptr;
+
+   void load_shader_type(const brw_builder &bld, brw_reg &dest) const;
+};
+
+

src/intel/compiler/meson.build

@@ -54,7 +54,6 @@ libintel_compiler_brw_files = files(
   'brw_from_nir.cpp',
   'brw_fs.cpp',
   'brw_fs.h',
-  'brw_fs_thread_payload.cpp',
   'brw_fs_visitor.cpp',
   'brw_generator.cpp',
   'brw_generator.h',
@@ -111,6 +110,8 @@ libintel_compiler_brw_files = files(
   'brw_schedule_instructions.cpp',
   'brw_simd_selection.cpp',
   'brw_spirv.c',
+  'brw_thread_payload.cpp',
+  'brw_thread_payload.h',
   'brw_validate.cpp',
   'brw_vue_map.c',
   'brw_workaround.cpp',