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radv: always clear the SR0/SR1 bits of the HTILE buffer

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To make sure the stencil compare state is properly initialized and
cleared when the driver performs a fast depth clear.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
This commit is contained in:
Samuel Pitoiset
2020-12-09 17:28:40 +01:00
committed by Marge Bot
parent 5c3b471c9f
commit f7f6e9ad56
3 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_cmd_buffer.c
+1 -1
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@@ -6000,7 +6000,7 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
struct radv_cmd_state *state = &cmd_buffer->state;
uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
uint32_t htile_value = vk_format_is_stencil(image->vk_format) ? 0xfffff3ff : 0xfffc000f;
VkClearDepthStencilValue value = {0};
struct radv_barrier_data barrier = {0};
src/amd/vulkan/radv_meta_clear.c
+1 -1
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@@ -953,7 +953,7 @@ radv_get_htile_fast_clear_value(const struct radv_image *image,
if (!image->planes[0].surface.has_stencil) {
clear_value = value.depth ? 0xfffffff0 : 0;
} else {
clear_value = value.depth ? 0xfffc0000 : 0;
clear_value = value.depth ? 0xfffc00f0 : 0xf0;
}
return clear_value;
src/amd/vulkan/radv_meta_resolve_cs.c
+1 -1
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@@ -998,7 +998,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
* buffer if it's resolved, otherwise this
* might break if the stencil has been cleared.
*/
clear_value = 0xfffff30f;
clear_value = 0xfffff3ff;
}
cmd_buffer->state.flush_bits |=