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i965/blorp: Prepare stencil sampling for gen8

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Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen
2016-04-07 18:50:56 +03:00
parent 708453952b
commit f7ab4e0cc4
2 changed files with 4 additions and 3 deletions
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3
src/mesa/drivers/dri/i965/brw_blorp.cpp
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@@ -94,7 +94,8 @@ brw_blorp_surface_info::set(struct brw_context *brw,
* program swizzle the coordinates.
*/
this->map_stencil_as_y_tiled = true;
this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
this->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
BRW_SURFACEFORMAT_R8_UNORM;
break;
case MESA_FORMAT_Z24_UNORM_X8_UINT:
/* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS

4
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
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@@ -711,9 +711,9 @@ brw_blorp_blit_program::compile(struct brw_context *brw,
alloc_regs();
compute_frag_coords();
/* Render target and texture hardware don't support W tiling. */
/* Render target and texture hardware don't support W tiling until Gen8. */
const bool rt_tiled_w = false;
const bool tex_tiled_w = false;
const bool tex_tiled_w = brw->gen >= 8 && key->src_tiled_w;
/* The address that data will be written to is determined by the
* coordinates supplied to the WM thread and the tiling and sample count of