r600g: use the new code for streamout flush as well
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@@ -1940,7 +1940,7 @@ void r600_context_streamout_begin(struct r600_context *ctx)
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ctx->num_cs_dw_streamout_end =
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12 + /* flush_vgt_streamout */
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util_bitcount(buffer_en) * 8 +
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8;
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3;
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r600_need_cs_space(ctx,
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12 + /* flush_vgt_streamout */
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@@ -2056,15 +2056,11 @@ void r600_context_streamout_end(struct r600_context *ctx)
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r600_set_streamout_enable(ctx, 0);
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}
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if (ctx->screen->family < CHIP_RV770) {
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
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cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
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if (ctx->screen->chip_class < R700) {
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r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv);
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} else {
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cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
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cs->buf[cs->cdw++] = flush_flags; /* CP_COHER_CNTL */
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cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
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cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
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cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
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ctx->atom_surface_sync.flush_flags |= flush_flags;
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r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
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}
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ctx->num_cs_dw_streamout_end = 0;
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@@ -2105,6 +2101,5 @@ void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_tar
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cs->buf[cs->cdw++] = 0; /* unused */
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cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
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cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size,
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RADEON_USAGE_READ);
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cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
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}
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