pco, pygen: add initial uvsw op boilerplate

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32258>

src/imagination/pco/pco_map.py

@@ -316,49 +316,7 @@ def op_map(op, hdr, isa_ops, srcs=[], iss=[], dests=[]):
    cop_name = op.cname.upper()
    op_maps[name] = OpMap(name, cop_name, igrp_mappings, None)
 
-
-op_map(O_NOP,
-   hdr=(I_IGRP_HDR_CONTROL, [
-      ('olchk', False),
-      ('w1p', False),
-      ('w0p', False),
-      ('cc', OM_EXEC_CND),
-      ('miscctl', False),
-      ('ctrlop', 'nop'),
-   ]),
-   isa_ops=[
-      ('ctrl', [(I_NOP, [])]),
-   ]
-)
-
-op_map(O_NOP_END,
-   hdr=(I_IGRP_HDR_CONTROL, [
-      ('olchk', False),
-      ('w1p', False),
-      ('w0p', False),
-      ('cc', OM_EXEC_CND),
-      ('miscctl', True),
-      ('ctrlop', 'nop'),
-   ]),
-   isa_ops=[
-      ('ctrl', [(I_NOP, [])]),
-   ]
-)
-
-op_map(O_WOP,
-   hdr=(I_IGRP_HDR_CONTROL, [
-      ('olchk', False),
-      ('w1p', False),
-      ('w0p', False),
-      ('cc', 'e1_zx'),
-      ('miscctl', 0),
-      ('ctrlop', 'wop'),
-   ]),
-   isa_ops=[
-      ('ctrl', [(I_WOP, [])]),
-   ]
-)
-
+# Main.
 op_map(O_MBYP0,
    hdr=(I_IGRP_HDR_MAIN, [
       ('oporg', 'p0'),
@@ -394,6 +352,7 @@ op_map(O_MBYP0,
    ]
 )
 
+# Bitwise
 op_map(O_MOVI32,
    hdr=(I_IGRP_HDR_BITWISE, [
       ('opcnt', 'p0'),
@@ -419,3 +378,46 @@ op_map(O_MOVI32,
       ('w0', 'dest[0]', 'ft1'),
    ]
 )
+
+# Control.
+op_map(O_WOP,
+   hdr=(I_IGRP_HDR_CONTROL, [
+      ('olchk', False),
+      ('w1p', False),
+      ('w0p', False),
+      ('cc', 'e1_zx'),
+      ('miscctl', 0),
+      ('ctrlop', 'wop'),
+   ]),
+   isa_ops=[
+      ('ctrl', [(I_WOP, [])]),
+   ]
+)
+
+op_map(O_NOP,
+   hdr=(I_IGRP_HDR_CONTROL, [
+      ('olchk', False),
+      ('w1p', False),
+      ('w0p', False),
+      ('cc', OM_EXEC_CND),
+      ('miscctl', False),
+      ('ctrlop', 'nop'),
+   ]),
+   isa_ops=[
+      ('ctrl', [(I_NOP, [])]),
+   ]
+)
+
+op_map(O_NOP_END,
+   hdr=(I_IGRP_HDR_CONTROL, [
+      ('olchk', False),
+      ('w1p', False),
+      ('w0p', False),
+      ('cc', OM_EXEC_CND),
+      ('miscctl', True),
+      ('ctrlop', 'nop'),
+   ]),
+   isa_ops=[
+      ('ctrl', [(I_NOP, [])]),
+   ]
+)

src/imagination/pco/pco_ops.h.py

@@ -55,7 +55,6 @@ enum pco_ref_mod {
    ${ref_mod.cname},
 % endfor
 };
-
 #endif /* PCO_OPS_H */"""
 
 def main():

src/imagination/pco/pco_ops.py

@@ -259,16 +259,25 @@ OM_PCK_FMT = op_mod_enum('pck_fmt', [
 ])
 OM_PHASE2END = op_mod('phase2end', BaseType.bool)
 
-# HW ops
-O_NOP = hw_op('nop', [OM_EXEC_CND])
-O_NOP_END = hw_op('nop.end', [OM_EXEC_CND])
-
-O_WOP = hw_op('wop')
+# Ops.
 
+## Main.
+O_FADD = hw_op('fadd', [OM_LP, OM_SAT], 1, 2, [], [[RM_ABS, RM_NEG, RM_FLR], [RM_ABS]])
 O_MBYP0 = hw_op('mbyp0', [OM_OLCHK, OM_EXEC_CND, OM_END, OM_ATOM, OM_RPT], 1, 1, [], [[RM_ABS, RM_NEG]])
 
-O_FADD = hw_op('fadd', [OM_LP, OM_SAT], 1, 2, [], [[RM_ABS, RM_NEG, RM_FLR], [RM_ABS]])
+## Backend.
+O_UVSW_WRITE = hw_op('uvsw.write', [OM_EXEC_CND, OM_RPT], 0, 2)
+O_UVSW_ENDTASK = hw_op('uvsw.endtask', [OM_END])
+
+## Bitwise.
+O_BBYP0BM = hw_direct_op('bbyp0bm', 2, 2)
 
 O_MOVI32 = pseudo_op('movi32', [OM_OLCHK, OM_EXEC_CND, OM_END, OM_ATOM, OM_RPT], 1, 1)
 
-O_BBYP0BM = hw_direct_op('bbyp0bm', 2, 2)
+## Control.
+O_WOP = hw_op('wop')
+O_NOP = hw_op('nop', [OM_EXEC_CND])
+O_NOP_END = hw_op('nop.end', [OM_EXEC_CND])
+
+# Pseudo-ops (unmapped).
+O_MOV = pseudo_op('mov', [OM_OLCHK, OM_EXEC_CND, OM_END, OM_ATOM, OM_RPT], 1, 1)