pco: initial image write support
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
This commit is contained in:
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Marge Bot
parent
3aacb6731c
commit
f54effa024
@@ -2532,30 +2532,7 @@ field_mappings=[
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('f16', 'f16'),
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('swap', 'swap'),
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('cachemode_ld', 'cachemode_smp_ld'),
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('w', 'smp_w', 0),
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])
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I_SMP_EXTB_W = bit_struct(
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name='smp_extb_w',
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bit_set=I_BACKEND,
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field_mappings=[
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('backend_op', 'backend_op', 'dma'),
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('fcnorm', 'fcnorm'),
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('drc', 'drc'),
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('dma_op', 'dma_op', 'smp'),
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('extb', 'extb', 1),
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('dmn', 'dmn'),
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('exta', 'exta', 0),
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('chan', 'chan'),
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('lodm', 'lodm'),
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('rsvd3', 'rsvd3_smp'),
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('f16', 'f16'),
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('swap', 'swap'),
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('cachemode_st', 'cachemode_smp_st'),
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('w', 'smp_w', 1),
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('w', 'smp_w'),
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])
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I_SMP_EXTAB = bit_struct(
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@@ -2586,38 +2563,7 @@ field_mappings=[
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('f16', 'f16'),
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('swap', 'swap'),
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('cachemode_ld', 'cachemode_smp_ld'),
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('w', 'smp_w', 0),
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])
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I_SMP_EXTAB_W = bit_struct(
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name='smp_extab_w',
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bit_set=I_BACKEND,
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field_mappings=[
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('backend_op', 'backend_op', 'dma'),
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('fcnorm', 'fcnorm'),
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('drc', 'drc'),
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('dma_op', 'dma_op', 'smp'),
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('extb', 'extb', 1),
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('dmn', 'dmn'),
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('exta', 'exta', 1),
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('chan', 'chan'),
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('lodm', 'lodm'),
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('pplod', 'pplod'),
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('proj', 'proj'),
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('sbmode', 'sbmode'),
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('nncoords', 'nncoords'),
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('sno', 'sno'),
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('soo', 'soo'),
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('tao', 'tao'),
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('rsvd3', 'rsvd3_smp'),
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('f16', 'f16'),
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('swap', 'swap'),
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('cachemode_st', 'cachemode_smp_st'),
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('w', 'smp_w', 1),
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('w', 'smp_w'),
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])
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I_ATOMIC = bit_struct(
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@@ -1369,7 +1369,8 @@ encode_map(O_SMP,
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('tao', OM_TAO),
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('f16', OM_F16),
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('swap', OM_SCHEDSWAP),
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('cachemode_ld', OM_MCU_CACHE_MODE_LD)
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('cachemode_ld', OM_MCU_CACHE_MODE_LD),
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('w', OM_WRT)
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]),
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(I_SMP_EXTA, [
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('fcnorm', OM_FCNORM),
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@@ -1387,7 +1388,8 @@ encode_map(O_SMP,
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], [
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(OM_F16, '== false'),
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(OM_SCHEDSWAP, '== PCO_SCHEDSWAP_NONE'),
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(OM_MCU_CACHE_MODE_LD, '== PCO_CACHEMODE_LD_NORMAL')
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(OM_MCU_CACHE_MODE_LD, '== PCO_CACHEMODE_LD_NORMAL'),
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(OM_WRT, '== false')
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]),
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(I_SMP_BRIEF, [
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('fcnorm', OM_FCNORM),
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@@ -1399,6 +1401,7 @@ encode_map(O_SMP,
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(OM_F16, '== false'),
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(OM_SCHEDSWAP, '== PCO_SCHEDSWAP_NONE'),
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(OM_MCU_CACHE_MODE_LD, '== PCO_CACHEMODE_LD_NORMAL'),
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(OM_WRT, '== false'),
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(OM_PPLOD, '== false'),
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(OM_PROJ, '== false'),
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(OM_SB_MODE, '== PCO_SB_MODE_NONE'),
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@@ -429,7 +429,7 @@ static void pco_nir_opt(pco_ctx *ctx, nir_shader *nir)
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};
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NIR_PASS(progress, nir, nir_opt_load_store_vectorize, &vectorize_opts);
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NIR_PASS(progress, nir, nir_opt_shrink_stores, true);
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NIR_PASS(progress, nir, nir_opt_shrink_stores, false);
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NIR_PASS(progress, nir, nir_opt_loop);
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NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
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@@ -755,13 +755,13 @@ static nir_def *lower_image(nir_builder *b, nir_instr *instr, void *cb_data)
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{
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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bool hw_array_support = false;
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bool hw_int_support = false;
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enum glsl_sampler_dim image_dim = nir_intrinsic_image_dim(intr);
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bool is_array = nir_intrinsic_image_array(intr);
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assert(!is_array);
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enum pipe_format format = nir_intrinsic_format(intr);
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nir_alu_type dest_type = nir_intrinsic_dest_type(intr);
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nir_alu_type type = intr->intrinsic == nir_intrinsic_image_deref_load
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? nir_intrinsic_dest_type(intr)
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: nir_intrinsic_src_type(intr);
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unsigned desc_set = nir_src_comp_as_uint(intr->src[0], 0);
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unsigned binding = nir_src_comp_as_uint(intr->src[0], 1);
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@@ -770,7 +770,15 @@ static nir_def *lower_image(nir_builder *b, nir_instr *instr, void *cb_data)
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nir_def *coords = !nir_src_is_undef(intr->src[1]) ? intr->src[1].ssa : NULL;
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nir_def *sample_index = !nir_src_is_undef(intr->src[2]) ? intr->src[2].ssa
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: NULL;
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nir_def *lod = !nir_src_is_undef(intr->src[3]) ? intr->src[3].ssa : NULL;
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nir_def *write_data = intr->intrinsic == nir_intrinsic_image_deref_store
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? intr->src[3].ssa
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: NULL;
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if (write_data) {
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assert(intr->num_components == 4);
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assert(write_data->num_components == 4);
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}
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ASSERTED bool msaa = image_dim == GLSL_SAMPLER_DIM_MS ||
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image_dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
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@@ -788,9 +796,7 @@ static nir_def *lower_image(nir_builder *b, nir_instr *instr, void *cb_data)
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.desc_set = PCO_POINT_SAMPLER,
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.binding = PCO_POINT_SAMPLER);
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unsigned num_coord_comps =
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glsl_get_sampler_dim_coordinate_components(image_dim) + !!is_array;
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unsigned num_coord_comps = nir_image_intrinsic_coord_components(intr);
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if (coords)
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coords = nir_trim_vector(b, coords, num_coord_comps);
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@@ -807,113 +813,32 @@ static nir_def *lower_image(nir_builder *b, nir_instr *instr, void *cb_data)
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&float_array_index,
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&int_array_index);
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nir_def *smp_data_comps[NIR_MAX_VEC_COMPONENTS];
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unsigned smp_data_comp_count = 0;
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pco_smp_flags smp_flags = {
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.dim = to_pco_dim(image_dim),
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.lod_mode = PCO_LOD_MODE_NORMAL,
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pco_smp_params params = {
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.tex_state = tex_state,
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.smp_state = smp_state,
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.dest_type = type,
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.sampler_dim = image_dim,
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.nncoords = true,
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.coords = float_coords,
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.ms_index = sample_index,
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.write_data = write_data,
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.sample_components = intr->intrinsic == nir_intrinsic_image_deref_load
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? intr->def.num_components
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: 0,
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};
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for (unsigned c = 0; c < num_coord_comps; ++c) {
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smp_data_comps[smp_data_comp_count++] =
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nir_channel(b, hw_int_support ? int_coords : float_coords, c);
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}
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nir_intrinsic_instr *smp = pco_emit_nir_smp(b, ¶ms);
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if (hw_array_support && int_array_index) {
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smp_data_comps[smp_data_comp_count++] =
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hw_int_support ? int_array_index : float_array_index;
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if (intr->intrinsic == nir_intrinsic_image_deref_load)
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return &smp->def;
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smp_flags.array = true;
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}
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bool lod_set = false;
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if (lod) {
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lod = nir_i2f32(b, lod);
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smp_data_comps[smp_data_comp_count++] = lod;
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smp_flags.pplod = true;
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smp_flags.lod_mode = PCO_LOD_MODE_REPLACE;
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lod_set = true;
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}
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if (!hw_array_support && int_array_index) {
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/* Set a per-pixel lod bias of 0 if none has been set yet. */
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if (!lod_set) {
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smp_data_comps[smp_data_comp_count++] = nir_imm_int(b, 0);
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smp_flags.pplod = true;
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smp_flags.lod_mode = PCO_LOD_MODE_BIAS;
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lod_set = true;
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}
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nir_def *tex_state_word[] = {
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[0] = nir_channel(b, tex_state, 0),
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[1] = nir_channel(b, tex_state, 1),
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[2] = nir_channel(b, tex_state, 2),
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[3] = nir_channel(b, tex_state, 3),
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};
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nir_def *base_addr_lo;
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nir_def *base_addr_hi;
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unpack_base_addr(b, tex_state_word, &base_addr_lo, &base_addr_hi);
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nir_def *array_index = int_array_index;
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assert(array_index);
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nir_def *array_size = STATE_UNPACK_ADD(b, tex_state_word, 2, 4, 11, 1);
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array_index = nir_uclamp(b, array_index, nir_imm_int(b, 0), array_size);
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nir_def *tex_meta = nir_load_tex_meta_pco(b,
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PCO_IMAGE_META_COUNT,
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elem,
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.desc_set = desc_set,
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.binding = binding);
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nir_def *array_stride =
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nir_channel(b, tex_meta, PCO_IMAGE_META_LAYER_SIZE);
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nir_def *array_offset = nir_imul(b, array_index, array_stride);
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nir_def *addr =
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nir_uadd64_2x32_lo(b, base_addr_lo, base_addr_hi, array_offset);
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smp_data_comps[smp_data_comp_count++] = nir_channel(b, addr, 0);
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smp_data_comps[smp_data_comp_count++] = nir_channel(b, addr, 1);
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smp_flags.tao = true;
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}
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if (sample_index) {
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nir_def *lookup = nir_bitfield_insert(b,
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nir_imm_int(b, 0),
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sample_index,
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nir_imm_int(b, 16),
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nir_imm_int(b, 3));
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smp_data_comps[smp_data_comp_count++] = lookup;
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smp_flags.sno = true;
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}
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/* Pad out the rest of the data words. */
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assert(smp_data_comp_count <= NIR_MAX_VEC_COMPONENTS);
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for (unsigned c = smp_data_comp_count; c < ARRAY_SIZE(smp_data_comps); ++c)
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smp_data_comps[c] = nir_imm_int(b, 0);
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nir_def *smp_data = nir_vec(b, smp_data_comps, ARRAY_SIZE(smp_data_comps));
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smp_flags.nncoords = true;
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smp_flags.integer = hw_int_support;
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smp_flags.fcnorm = nir_alu_type_get_base_type(dest_type) == nir_type_float;
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return nir_smp_pco(b,
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intr->def.num_components,
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smp_data,
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tex_state,
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smp_state,
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.smp_flags_pco = smp_flags._,
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.range = smp_data_comp_count);
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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}
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static bool is_image(const nir_instr *instr, UNUSED const void *cb_data)
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@@ -924,6 +849,7 @@ static bool is_image(const nir_instr *instr, UNUSED const void *cb_data)
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_image_deref_load:
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case nir_intrinsic_image_deref_store:
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return true;
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default:
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@@ -170,6 +170,7 @@ static nir_def *lower_vk(nir_builder *b, nir_instr *instr, void *cb_data)
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return lower_load_vulkan_descriptor(b, intr, common);
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case nir_intrinsic_image_deref_load:
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case nir_intrinsic_image_deref_store:
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return lower_image_derefs(b, intr, common);
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default:
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@@ -207,6 +208,7 @@ static bool is_vk(const nir_instr *instr, UNUSED const void *cb_data)
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switch (intr->intrinsic) {
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case nir_intrinsic_load_vulkan_descriptor:
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case nir_intrinsic_image_deref_load:
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case nir_intrinsic_image_deref_store:
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return true;
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default:
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@@ -189,6 +189,7 @@ OM_PPLOD = op_mod('pplod', BaseType.bool)
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OM_TAO = op_mod('tao', BaseType.bool)
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OM_SOO = op_mod('soo', BaseType.bool)
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OM_SNO = op_mod('sno', BaseType.bool)
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OM_WRT = op_mod('wrt', BaseType.bool)
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OM_SB_MODE = op_mod_enum('sb_mode', [
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('none', ''),
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('rawdata', 'rawdata'),
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@@ -384,7 +385,7 @@ O_ATOMIC = hw_op('atomic', [OM_OLCHK, OM_EXEC_CND, OM_END, OM_ATOM_OP], 1, 2)
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O_SMP = hw_op('smp', OM_ALU_RPT1 + [OM_DIM, OM_PROJ, OM_FCNORM, OM_NNCOORDS,
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OM_LOD_MODE, OM_PPLOD, OM_TAO, OM_SOO,
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OM_SNO, OM_SB_MODE, OM_MCU_CACHE_MODE_LD,
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OM_SNO, OM_WRT, OM_SB_MODE, OM_MCU_CACHE_MODE_LD,
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OM_ARRAY, OM_INTEGER, OM_SCHEDSWAP, OM_F16], 1, 6)
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O_ALPHATST = hw_op('alphatst', OM_ALU_RPT1, 1, 4)
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@@ -1010,6 +1010,10 @@ static pco_instr *lower_smp(trans_ctx *tctx,
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/* Destination and chans should be correct. */
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break;
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case nir_intrinsic_smp_write_pco:
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chans = 4;
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break;
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default:
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UNREACHABLE("");
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}
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@@ -1035,7 +1039,8 @@ static pco_instr *lower_smp(trans_ctx *tctx,
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.sno = smp_flags.sno,
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.sb_mode = sb_mode,
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.array = smp_flags.array,
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.integer = smp_flags.integer);
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.integer = smp_flags.integer,
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.wrt = smp_flags.wrt);
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return smp;
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}
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@@ -1287,6 +1292,7 @@ static pco_instr *trans_intr(trans_ctx *tctx, nir_intrinsic_instr *intr)
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case nir_intrinsic_smp_coeffs_pco:
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case nir_intrinsic_smp_pco:
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case nir_intrinsic_smp_write_pco:
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instr = lower_smp(tctx, intr, &dest, src[0], src[1], src[2]);
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break;
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