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pan/bi: Register allocate BLEND dest on Valhall

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On Bifrost, BLEND writes to the link register, acting like a function call. On
Valhall, BLEND does not write anything. But the BLEND instruction in our IR is a
pseudo-instruction with Bifrost semantics, expanding to a multi-instruction
sequence on Valhall. So it's not worth special casing Valhall in instruction
selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
This commit is contained in:
Alyssa Rosenzweig
2022-07-21 14:53:35 -04:00
committed by Marge Bot
parent 1bca6059b2
commit f52de4621a
3 changed files with 16 additions and 21 deletions
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src/panfrost/bifrost/bifrost_compile.c
+8 -13
View File
@@ -791,9 +791,6 @@ static void
bi_emit_blend_op(bi_builder *b, bi_index rgba, nir_alu_type T,
bi_index rgba2, nir_alu_type T2, unsigned rt)
{
/* On Valhall, BLEND does not encode the return address */
bool bifrost = b->shader->arch <= 8;
/* Reads 2 or 4 staging registers to cover the input */
unsigned size = nir_alu_type_get_type_size(T);
unsigned size_2 = nir_alu_type_get_type_size(T2);
@@ -819,21 +816,19 @@ bi_emit_blend_op(bi_builder *b, bi_index rgba, nir_alu_type T,
/* Blend descriptor comes from the compile inputs */
/* Put the result in r0 */
bi_blend_to(b, bifrost ? bi_temp(b->shader) : bi_null(), rgba,
bi_coverage(b),
bi_imm_u32(blend_desc),
bi_imm_u32(blend_desc >> 32),
bi_null(), regfmt, sr_count, 0);
bi_blend_to(b, bi_temp(b->shader), rgba, bi_coverage(b),
bi_imm_u32(blend_desc),
bi_imm_u32(blend_desc >> 32),
bi_null(), regfmt, sr_count, 0);
} else {
/* Blend descriptor comes from the FAU RAM. By convention, the
* return address on Bifrost is stored in r48 and will be used
* by the blend shader to jump back to the fragment shader */
bi_blend_to(b, bifrost ? bi_temp(b->shader) : bi_null(), rgba,
bi_coverage(b),
bi_fau(BIR_FAU_BLEND_0 + rt, false),
bi_fau(BIR_FAU_BLEND_0 + rt, true),
rgba2, regfmt, sr_count, sr_count_2);
bi_blend_to(b, bi_temp(b->shader), rgba, bi_coverage(b),
bi_fau(BIR_FAU_BLEND_0 + rt, false),
bi_fau(BIR_FAU_BLEND_0 + rt, true),
rgba2, regfmt, sr_count, sr_count_2);
}
assert(rt < 8);
src/panfrost/bifrost/valhall/test/test-mark-last.cpp
+3 -3
View File
@@ -121,18 +121,18 @@ TEST(MarkLast, Half64) {
TEST(MarkLast, RegisterBlendDescriptor) {
CASE({
bi_blend_to(b, bi_null(), R(0), DR(60), DR(4), DR(5), bi_null(),
bi_blend_to(b, R(48), R(0), DR(60), DR(4), DR(5), bi_null(),
BI_REGISTER_FORMAT_F32, 4, 0);
});
CASE({
bi_blend_to(b, bi_null(), R(0), DR(60), R(4), R(5), bi_null(),
bi_blend_to(b, R(48), R(0), DR(60), R(4), R(5), bi_null(),
BI_REGISTER_FORMAT_F32, 4, 0);
bi_fadd_f32_to(b, R(4), DR(4), DR(7));
});
CASE({
bi_blend_to(b, bi_null(), R(0), DR(60), R(4), R(5), bi_null(),
bi_blend_to(b, R(48), R(0), DR(60), R(4), R(5), bi_null(),
BI_REGISTER_FORMAT_F32, 4, 0);
bi_fadd_f32_to(b, R(4), DR(5), DR(7));
});
src/panfrost/bifrost/valhall/va_pack.c
+5 -5
View File
@@ -902,9 +902,6 @@ va_lower_branch_target(bi_context *ctx, bi_block *start, bi_instr *I)
static void
va_lower_blend(bi_context *ctx)
{
/* Link register (ABI between fragment and blend shaders) */
bi_index lr = bi_register(48);
/* Program counter for *next* instruction */
bi_index pc = bi_fau(BIR_FAU_PROGRAM_COUNTER, false);
@@ -916,10 +913,13 @@ va_lower_blend(bi_context *ctx)
unsigned prolog_length = 2 * 8;
/* By ABI, r48 is the link register shared with blend shaders */
assert(bi_is_equiv(I->dest[0], bi_register(48)));
if (I->flow == VA_FLOW_END)
bi_iadd_imm_i32_to(&b, lr, va_zero_lut(), 0);
bi_iadd_imm_i32_to(&b, I->dest[0], va_zero_lut(), 0);
else
bi_iadd_imm_i32_to(&b, lr, pc, prolog_length - 8);
bi_iadd_imm_i32_to(&b, I->dest[0], pc, prolog_length - 8);
bi_branchzi(&b, va_zero_lut(), I->src[3], BI_CMPF_EQ);