radeonsi: drop some cayman remnants
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <deathsimple@vodafone.de>
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committed by
Christian König
parent
22ae062fa1
commit
f1a3de5e9d
@@ -39,7 +39,6 @@ struct winsys_handle;
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enum radeon_family {
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CHIP_UNKNOWN,
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CHIP_CAYMAN,
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CHIP_TAHITI,
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CHIP_PITCAIRN,
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CHIP_VERDE,
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@@ -47,7 +46,6 @@ enum radeon_family {
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};
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enum chip_class {
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CAYMAN,
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TAHITI,
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};
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@@ -45,12 +45,7 @@ void si_get_backend_mask(struct r600_context *ctx)
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if (ctx->screen->info.r600_backend_map_valid) {
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unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
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unsigned backend_map = ctx->screen->info.r600_backend_map;
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unsigned item_width, item_mask;
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if (ctx->chip_class >= CAYMAN) {
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item_width = 4;
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item_mask = 0x7;
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}
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unsigned item_width = 4, item_mask = 0x7;
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while(num_tile_pipes--) {
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i = backend_map & item_mask;
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@@ -1801,18 +1801,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
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tl_y = 0;
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br_x = state->width;
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br_y = state->height;
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#if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
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/* EG hw workaround */
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if (br_x == 0)
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tl_x = 1;
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if (br_y == 0)
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tl_y = 1;
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/* cayman hw workaround */
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if (rctx->chip_class == CAYMAN) {
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if (br_x == 1 && br_y == 1)
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br_x = 2;
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}
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#endif
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tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
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br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
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@@ -56,10 +56,8 @@ void si_context_streamout_begin(struct r600_context *ctx)
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util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
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ctx->num_cs_dw_streamout_end, TRUE);
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if (ctx->chip_class >= CAYMAN) {
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evergreen_flush_vgt_streamout(ctx);
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evergreen_set_streamout_enable(ctx, buffer_en);
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}
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evergreen_flush_vgt_streamout(ctx);
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evergreen_set_streamout_enable(ctx, buffer_en);
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for (i = 0; i < ctx->num_so_targets; i++) {
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#if 0
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