radeonsi: drop some cayman remnants

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
This commit is contained in:
Alex Deucher
2012-09-28 11:06:48 -04:00
committed by Christian König
parent 22ae062fa1
commit f1a3de5e9d
4 changed files with 4 additions and 24 deletions
-2
View File
@@ -39,7 +39,6 @@ struct winsys_handle;
enum radeon_family {
CHIP_UNKNOWN,
CHIP_CAYMAN,
CHIP_TAHITI,
CHIP_PITCAIRN,
CHIP_VERDE,
@@ -47,7 +46,6 @@ enum radeon_family {
};
enum chip_class {
CAYMAN,
TAHITI,
};
@@ -45,12 +45,7 @@ void si_get_backend_mask(struct r600_context *ctx)
if (ctx->screen->info.r600_backend_map_valid) {
unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
unsigned backend_map = ctx->screen->info.r600_backend_map;
unsigned item_width, item_mask;
if (ctx->chip_class >= CAYMAN) {
item_width = 4;
item_mask = 0x7;
}
unsigned item_width = 4, item_mask = 0x7;
while(num_tile_pipes--) {
i = backend_map & item_mask;
+1 -12
View File
@@ -1801,18 +1801,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
tl_y = 0;
br_x = state->width;
br_y = state->height;
#if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
/* EG hw workaround */
if (br_x == 0)
tl_x = 1;
if (br_y == 0)
tl_y = 1;
/* cayman hw workaround */
if (rctx->chip_class == CAYMAN) {
if (br_x == 1 && br_y == 1)
br_x = 2;
}
#endif
tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
@@ -56,10 +56,8 @@ void si_context_streamout_begin(struct r600_context *ctx)
util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
ctx->num_cs_dw_streamout_end, TRUE);
if (ctx->chip_class >= CAYMAN) {
evergreen_flush_vgt_streamout(ctx);
evergreen_set_streamout_enable(ctx, buffer_en);
}
evergreen_flush_vgt_streamout(ctx);
evergreen_set_streamout_enable(ctx, buffer_en);
for (i = 0; i < ctx->num_so_targets; i++) {
#if 0