i965: Drop mt->levels[].width/height.

It often confused people because it was unclear on whether it was the
physical or logical, and people needed the other one as well.  We can
recompute it trivially using the minify() macro, clarifying which value is
being used and making getting the other value obvious.

v2: Fix a pasteo in intel_blit.c's dst flip.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/mesa/drivers/dri/i965/brw_blorp.cpp

@@ -68,8 +68,8 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
    this->mt = mt;
    this->level = level;
    this->layer = layer;
-   this->width = mt->level[level].width;
-   this->height = mt->level[level].height;
+   this->width = minify(mt->physical_width0, level);
+   this->height = minify(mt->physical_height0, level);
 
    intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
 }

src/mesa/drivers/dri/i965/brw_clear.c

@@ -155,7 +155,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
        *        width of the map (LOD0) is not multiple of 16, fast clear
        *        optimization must be disabled.
        */
-      if (brw->gen == 6 && (mt->level[depth_irb->mt_level].width % 16) != 0)
+      if (brw->gen == 6 && (minify(mt->physical_width0,
+                                   depth_irb->mt_level) % 16) != 0)
 	 return false;
       /* FALLTHROUGH */
 

src/mesa/drivers/dri/i965/brw_tex_layout.c

@@ -197,8 +197,7 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
       unsigned img_height;
 
-      intel_miptree_set_level_info(mt, level, x, y, width,
-				   height, depth);
+      intel_miptree_set_level_info(mt, level, x, y, depth);
 
       img_height = ALIGN(height, mt->align_h);
       if (mt->compressed)
@@ -281,7 +280,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
       if (mt->target == GL_TEXTURE_CUBE_MAP)
          DL = 6;
 
-      intel_miptree_set_level_info(mt, level, 0, 0, WL, HL, DL);
+      intel_miptree_set_level_info(mt, level, 0, 0, DL);
 
       for (unsigned q = 0; q < DL; q++) {
          unsigned x = (q % (1 << level)) * wL;

src/mesa/drivers/dri/i965/intel_blit.c

@@ -215,10 +215,10 @@ intel_miptree_blit(struct brw_context *brw,
    intel_miptree_resolve_color(brw, dst_mt);
 
    if (src_flip)
-      src_y = src_mt->level[src_level].height - src_y - height;
+      src_y = minify(src_mt->physical_height0, src_level) - src_y - height;
 
    if (dst_flip)
-      dst_y = dst_mt->level[dst_level].height - dst_y - height;
+      dst_y = minify(dst_mt->physical_height0, dst_level) - dst_y - height;
 
    int src_pitch = src_mt->region->pitch;
    if (src_flip != dst_flip)

src/mesa/drivers/dri/i965/intel_mipmap_tree.c

@@ -867,24 +867,10 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
     * minification.  This will also catch images not present in the
     * tree, changed targets, etc.
     */
-   if (mt->target == GL_TEXTURE_2D_MULTISAMPLE ||
-         mt->target == GL_TEXTURE_2D_MULTISAMPLE_ARRAY) {
-      /* nonzero level here is always bogus */
-      assert(level == 0);
-
-      if (width != mt->logical_width0 ||
-            height != mt->logical_height0 ||
-            depth != mt->logical_depth0) {
-         return false;
-      }
-   }
-   else {
-      /* all normal textures, renderbuffers, etc */
-      if (width != mt->level[level].width ||
-          height != mt->level[level].height ||
-          depth != mt->level[level].depth) {
-         return false;
-      }
+   if (width != minify(mt->logical_width0, level) ||
+       height != minify(mt->logical_height0, level) ||
+       depth != mt->level[level].depth) {
+      return false;
    }
 
    if (image->NumSamples != mt->num_samples)
@@ -897,17 +883,14 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
 void
 intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
 			     GLuint level,
-			     GLuint x, GLuint y,
-			     GLuint w, GLuint h, GLuint d)
+			     GLuint x, GLuint y, GLuint d)
 {
-   mt->level[level].width = w;
-   mt->level[level].height = h;
    mt->level[level].depth = d;
    mt->level[level].level_x = x;
    mt->level[level].level_y = y;
 
-   DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__,
-       level, w, h, d, x, y);
+   DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__,
+       level, d, x, y);
 
    assert(mt->level[level].slice == NULL);
 
@@ -1049,8 +1032,8 @@ intel_miptree_copy_slice(struct brw_context *brw,
 
 {
    mesa_format format = src_mt->format;
-   uint32_t width = src_mt->level[level].width;
-   uint32_t height = src_mt->level[level].height;
+   uint32_t width = minify(src_mt->physical_width0, level);
+   uint32_t height = minify(src_mt->physical_height0, level);
    int slice;
 
    if (face > 0)
@@ -1255,7 +1238,8 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw,
    assert(mt->hiz_mt);
 
    if (brw->is_haswell) {
-      const struct intel_mipmap_level *l = &mt->level[level];
+      uint32_t width = minify(mt->physical_width0, level);
+      uint32_t height = minify(mt->physical_height0, level);
 
       /* Disable HiZ for LOD > 0 unless the width is 8 aligned
        * and the height is 4 aligned. This allows our HiZ support
@@ -1263,7 +1247,7 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw,
        * we can grow the width & height to allow the HiZ op to
        * force the proper size alignments.
        */
-      if (level > 0 && ((l->width & 7) || (l->height & 3))) {
+      if (level > 0 && ((width & 7) || (height & 3))) {
          return false;
       }
    }

src/mesa/drivers/dri/i965/intel_mipmap_tree.h

@@ -104,8 +104,6 @@ struct intel_mipmap_level
    GLuint level_x;
    /** Offset to this miptree level, used in computing y_offset. */
    GLuint level_y;
-   GLuint width;
-   GLuint height;
 
    /**
     * \brief Number of 2D slices in this miplevel.
@@ -538,8 +536,7 @@ intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt,
 
 void intel_miptree_set_level_info(struct intel_mipmap_tree *mt,
                                   GLuint level,
-                                  GLuint x, GLuint y,
-                                  GLuint w, GLuint h, GLuint d);
+                                  GLuint x, GLuint y, GLuint d);
 
 void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt,
                                     GLuint level,

src/mesa/drivers/dri/i965/intel_screen.c

@@ -333,8 +333,8 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
    intel_region_get_tile_masks(mt->region, &mask_x, &mask_y, false);
    intel_miptree_get_image_offset(mt, level, zoffset, &draw_x, &draw_y);
 
-   image->width = mt->level[level].width;
-   image->height = mt->level[level].height;
+   image->width = minify(mt->physical_width0, level);
+   image->height = minify(mt->physical_height0, level);
    image->tile_x = draw_x & mask_x;
    image->tile_y = draw_y & mask_y;