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intel/isl: Consolidate some tiling checks for CCS

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Filter out X-tiling early to avoid an assert failure in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29659>
This commit is contained in:
Nanley Chery
2024-05-01 22:33:10 -04:00
committed by Marge Bot
parent 26802b3224
commit eff2fab0bc
1 changed files with 16 additions and 21 deletions
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src/intel/isl/isl.c
+16 -21
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@@ -2994,12 +2994,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
*
* - Support is limited to tiled render targets.
*
* From the Skylake documentation, it is made clear that X-tiling is no
* longer supported:
*
* - MCS and Lossless compression is supported for
* TiledY/TileYs/TileYf non-MSRTs only.
*
* From the BSpec (44930) for Gfx12:
*
* Linear CCS is only allowed for Untyped Buffers but only via HDC
@@ -3011,6 +3005,22 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (surf->tiling == ISL_TILING_LINEAR)
return false;
/* From the SKL PRMs, Volume 7: MCS Buffer for Render Target(s),
*
* - Note: Lossless Color Compression can only be applied to Surfaces
* which are TileY, TileYs, or TileYf.
*
* From the ACM PRMs, Volume 9: MCS/CCS Buffers for Render Target(s),
*
* - Note: Lossless Color Compression can only be applied to Surfaces
* which are Linear, Tile4, or Tile64. (TileY/TileYF/TileYS on older
* devices)
*
* It is made clear that X-tiling is no longer supported on SKL+.
*/
if (ISL_GFX_VER(dev) >= 9 && surf->tiling == ISL_TILING_X)
return false;
/* SKL PRMs, Volume 5: Memory Views, Tiling and Mip Tails for 2D Surfaces:
*
* "Lossless compression must not be used on surfaces which have MIP
@@ -3159,12 +3169,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
isl_tiling_is_64(surf->tiling)) &&
(format_bpb == 64 || format_bpb == 128))
return false;
/* TODO: Handle the other tiling formats */
if (surf->tiling != ISL_TILING_Y0 &&
surf->tiling != ISL_TILING_4 &&
!isl_tiling_is_64(surf->tiling))
return false;
} else {
/* ISL_GFX_VER(dev) < 12 */
if (surf->samples > 1)
@@ -3200,15 +3204,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (ISL_GFX_VER(dev) <= 7 &&
(surf->levels > 1 || surf->logical_level0_px.array_len > 1))
return false;
/* From the Skylake documentation, it is made clear that X-tiling is no
* longer supported:
*
* - MCS and Lossless compression is supported for
* TiledY/TileYs/TileYf non-MSRTs only.
*/
if (ISL_GFX_VER(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling))
return false;
}
return true;