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radv: add support for BO metadata on GFX12

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33193>
This commit is contained in:
Samuel Pitoiset
2025-01-24 09:30:44 +01:00
committed by Marge Bot
parent 8fd0eda0cf
commit ee4a1021d1
3 changed files with 38 additions and 5 deletions
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src/amd/vulkan/radv_image.c
+16 -3
View File
@@ -120,7 +120,9 @@ radv_surface_has_scanout(struct radv_device *device, const struct radv_image_cre
const struct radv_physical_device *pdev = radv_device_physical(device);
if (info->bo_metadata) {
if (pdev->info.gfx_level >= GFX9)
if (pdev->info.gfx_level >= GFX12) {
return info->bo_metadata->u.gfx12.scanout;
} else if (pdev->info.gfx_level >= GFX9)
return info->bo_metadata->u.gfx9.scanout;
else
return info->bo_metadata->u.legacy.scanout;
@@ -472,7 +474,12 @@ radv_patch_surface_from_metadata(struct radv_device *device, struct radeon_surf
surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
if (pdev->info.gfx_level >= GFX9) {
if (pdev->info.gfx_level >= GFX12) {
surface->u.gfx9.swizzle_mode = md->u.gfx12.swizzle_mode;
surface->u.gfx9.color.dcc.max_compressed_block_size = md->u.gfx12.dcc_max_compressed_block;
surface->u.gfx9.color.dcc_data_format = md->u.gfx12.dcc_data_format;
surface->u.gfx9.color.dcc_number_type = md->u.gfx12.dcc_number_type;
} else if (pdev->info.gfx_level >= GFX9) {
if (md->u.gfx9.swizzle_mode > 0)
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
else
@@ -784,7 +791,13 @@ radv_init_metadata(struct radv_device *device, struct radv_image *image, struct
memset(metadata, 0, sizeof(*metadata));
if (pdev->info.gfx_level >= GFX9) {
if (pdev->info.gfx_level >= GFX12) {
metadata->u.gfx12.swizzle_mode = surface->u.gfx9.swizzle_mode;
metadata->u.gfx12.dcc_max_compressed_block = surface->u.gfx9.color.dcc.max_compressed_block_size;
metadata->u.gfx12.dcc_number_type = surface->u.gfx9.color.dcc_number_type;
metadata->u.gfx12.dcc_data_format = surface->u.gfx9.color.dcc_data_format;
metadata->u.gfx12.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
} else if (pdev->info.gfx_level >= GFX9) {
uint64_t dcc_offset =
image->bindings[0].offset + (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset);
metadata->u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode;
src/amd/vulkan/radv_radeon_winsys.h
+8
View File
@@ -145,6 +145,14 @@ struct radeon_bo_metadata {
bool dcc_independent_128b_blocks;
unsigned dcc_max_compressed_block_size;
} gfx9;
struct {
unsigned swizzle_mode : 3;
unsigned dcc_max_compressed_block : 3;
unsigned dcc_data_format : 6;
unsigned dcc_number_type : 3;
bool scanout;
} gfx12;
} u;
/* Additional metadata associated with the buffer, in bytes.
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+14 -2
View File
@@ -972,7 +972,13 @@ radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys *_ws, struct radeon_wins
struct amdgpu_bo_metadata metadata = {0};
uint64_t tiling_flags = 0;
if (ws->info.gfx_level >= GFX9) {
if (ws->info.gfx_level >= GFX12) {
tiling_flags |= AMDGPU_TILING_SET(GFX12_SWIZZLE_MODE, md->u.gfx12.swizzle_mode);
tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_MAX_COMPRESSED_BLOCK, md->u.gfx12.dcc_max_compressed_block);
tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_NUMBER_TYPE, md->u.gfx12.dcc_number_type);
tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_DATA_FORMAT, md->u.gfx12.dcc_data_format);
tiling_flags |= AMDGPU_TILING_SET(GFX12_SCANOUT, md->u.gfx12.scanout);
} else if (ws->info.gfx_level >= GFX9) {
tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b);
tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max);
@@ -1023,7 +1029,13 @@ radv_amdgpu_winsys_bo_get_metadata(struct radeon_winsys *_ws, struct radeon_wins
uint64_t tiling_flags = info.metadata.tiling_info;
if (ws->info.gfx_level >= GFX9) {
if (ws->info.gfx_level >= GFX12) {
md->u.gfx12.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, GFX12_SWIZZLE_MODE);
md->u.gfx12.dcc_max_compressed_block = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
md->u.gfx12.dcc_data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
md->u.gfx12.dcc_number_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
md->u.gfx12.scanout = AMDGPU_TILING_GET(tiling_flags, GFX12_SCANOUT);
} else if (ws->info.gfx_level >= GFX9) {
md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT);
} else {