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pvr: Update for firmware 1.17@6256262

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Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17139>
This commit is contained in:
Sarah Walker
2022-05-27 14:51:39 +01:00
committed by Marge Bot
parent ee9c3d2625
commit ee491967c3
4 changed files with 126 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/imagination/vulkan/winsys/pvrsrvkm/fw-api/pvr_rogue_fwif.h
+111 -56
View File
@@ -154,25 +154,37 @@ struct rogue_fwif_ta_regs {
uint64_t vdm_ctrl_stream_base;
uint64_t tpu_border_colour_table;
/* Only used when feature VDM_DRAWINDIRECT present. */
uint64_t vdm_draw_indirect0;
/* Only used when feature VDM_DRAWINDIRECT present. */
uint32_t vdm_draw_indirect1;
uint32_t ppp_ctrl;
uint32_t te_psg;
/* FIXME: HIGH: FIX_HW_BRN_49927 changes the structure's layout, given we
* are supporting Features/ERNs/BRNs at runtime, we need to look into this
* and find a solution to keep layout intact.
*/
/* Available if FIX_HW_BRN_49927 is present. */
/* Only used when BRN 49927 present. */
uint32_t tpu;
uint32_t vdm_context_resume_task0_size;
/* Only used when feature VDM_OBJECT_LEVEL_LLS present. */
uint32_t vdm_context_resume_task3_size;
/* FIXME: HIGH: FIX_HW_BRN_56279 changes the structure's layout, given we
* are supporting Features/ERNs/BRNs at runtime, we need to look into this
* and find a solution to keep layout intact.
*/
/* Available if FIX_HW_BRN_56279 is present. */
/* Only used when BRN 56279 or BRN 67381 present. */
uint32_t pds_ctrl;
uint32_t view_idx;
/* Only used when feature TESSELLATION present */
uint32_t pds_coeff_free_prog;
uint32_t padding;
};
/**
* \brief Dummy region header registers.
*/
/* Only used when BRN 44455 or BRN 63027 present. */
struct rogue_fwif_dummy_rgnhdr_init_geom_regs {
uint64_t te_psgregion_addr;
};
/**
@@ -203,6 +215,15 @@ struct rogue_fwif_cmd_ta {
* to go through.
*/
struct rogue_fwif_ufo partial_render_ta_3d_fence;
/* Only used when BRN 44455 or BRN 63027 present. */
struct rogue_fwif_dummy_rgnhdr_init_geom_regs
ALIGN_ATTR(8) dummy_rgnhdr_init_geom_regs;
/* Only used when BRN 61484 or BRN 66333 present. */
uint32_t brn61484_66333_live_rt;
uint32_t padding;
};
static_assert(
@@ -224,38 +245,34 @@ struct rogue_fwif_3d_regs {
* section.
*/
uint32_t usc_pixel_output_ctrl;
/* FIXME: HIGH: RGX_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL changes the
* structure's layout.
*/
#define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U
uint32_t usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL];
uint32_t isp_bgobjdepth;
uint32_t isp_bgobjvals;
uint32_t isp_aa;
/* Only used when feature S7_TOP_INFRASTRUCTURE present. */
uint32_t isp_xtp_pipe_enable;
uint32_t isp_ctl;
/* FIXME: HIGH: FIX_HW_BRN_49927 changes the structure's layout, given we
* are supporting Features/ERNs/BRNs at runtime, we need to look into this
* and find a solution to keep layout intact.
*/
/* Available if FIX_HW_BRN_49927 is present. */
/* Only used when feature CLUSTER_GROUPING present. */
uint32_t tpu;
uint32_t event_pixel_pds_info;
/* FIXME: HIGH: RGX_FEATURE_CLUSTER_GROUPING changes the structure's
* layout.
*/
uint32_t pixel_phantom;
uint32_t view_idx;
uint32_t event_pixel_pds_data;
/* FIXME: HIGH: MULTIBUFFER_OCLQRY changes the structure's layout.
* Commenting out for now as it's not supported by 4.V.2.51.
*/
/* uint32_t isp_oclqry_stride; */
/* Only used when BRN 65101 present. */
uint32_t brn65101_event_pixel_pds_data;
/* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */
uint32_t isp_oclqry_stride;
/* All values below the ALIGN_ATTR(8) must be 64 bit. */
uint64_t ALIGN_ATTR(8) isp_scissor_base;
@@ -264,22 +281,40 @@ struct rogue_fwif_3d_regs {
uint64_t isp_zlsctl;
uint64_t isp_zload_store_base;
uint64_t isp_stencil_load_store_base;
/* FIXME: HIGH: RGX_FEATURE_ZLS_SUBTILE changes the structure's layout. */
/* Only used when feature ZLS_SUBTILE present. */
uint64_t isp_zls_pixels;
/* FIXME: HIGH: RGX_HW_REQUIRES_FB_CDC_ZLS_SETUP changes the structure's
* layout.
/*
* Only used when feature FBCDC_ALGORITHM present and value < 3 or feature
* FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must
* not be present.
*/
uint64_t deprecated;
uint64_t fb_cdc_zls;
/* FIXME: HIGH: RGX_PBE_WORDS_REQUIRED_FOR_RENDERS changes the structure's
* layout.
*/
#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 2U
#define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U
uint64_t pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS];
uint64_t tpu_border_colour_table;
uint64_t pds_bgnd[3U];
/* Only used when BRN 65101 present. */
uint64_t pds_bgnd_brn65101[3U];
uint64_t pds_pr_bgnd[3U];
/* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */
uint64_t rgx_cr_blackpearl_fix;
/* Only used when BRN 62850 or 62865 present. */
uint64_t isp_dummy_stencil_store_base;
/* Only used when BRN 66193 present. */
uint64_t isp_dummy_depth_store_base;
/* Only used when BRN 67182 present. */
uint32_t rgnhdr_single_rt_size;
/* Only used when BRN 67182 present. */
uint32_t rgnhdr_scratch_offset;
};
/**
@@ -305,11 +340,17 @@ struct rogue_fwif_cmd_3d {
/** Stride IN BYTES for S-Buffer in case of RTAs. */
uint32_t sls_stride;
/* FIXME: HIGH: RGX_FEATURE_GPU_MULTICORE_SUPPORT changes the structure's
* layout. Commenting out for now as it's not supported by 4.V.2.51.
*/
/* Only used when SUPPORT_STRIP_RENDERING present. */
uint8_t ui8FrameStripBuffer;
/* Only used when SUPPORT_STRIP_RENDERING present. */
uint8_t ui8FrameStripIndex;
/* Only used when SUPPORT_STRIP_RENDERING present. */
uint8_t ui8FrameStripMode;
/* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */
/* uint32_t execute_count; */
uint32_t execute_count;
uint32_t padding;
};
static_assert(
@@ -426,26 +467,36 @@ struct rogue_fwif_cmd_abort {
struct rogue_fwif_cdm_regs {
uint64_t tpu_border_colour_table;
/* FIXME: HIGH: RGX_FEATURE_COMPUTE_MORTON_CAPABLE changes the structure's
* layout.
*/
/* Only used when feature COMPUTE_MORTON_CAPABLE present. */
uint64_t cdm_item;
/* FIXME: HIGH: RGX_FEATURE_CLUSTER_GROUPING changes the structure's layout.
*/
/* Only used when feature CLUSTER_GROUPING present. */
uint64_t compute_cluster;
/* FIXME: HIGH: RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS changes the structure's
* layout. Commenting out for now as it's not supported by 4.V.2.51.
*/
/* uint64_t tpu_tag_cdm_ctrl; */
uint64_t cdm_ctrl_stream_base;
uint64_t cdm_contex_state_base_addr;
/* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */
uint64_t tpu_tag_cdm_ctrl;
/* FIXME: HIGH: FIX_HW_BRN_49927 changes the structure's layout, given we
* are supporting Features/ERNs/BRNs at runtime, we need to look into this
* and find a solution to keep layout intact.
/* Only used when feature CDM_USER_MODE_QUEUE present. */
uint64_t cdm_cb_queue;
/*
* Only used when feature CDM_USER_MODE_QUEUE is present and
* SUPPORT_TRUSTED_DEVICE is present and SUPPORT_SECURE_ALLOC_KM is not
* present.
*/
/* Available if FIX_HW_BRN_49927 is present. */
uint64_t cdm_cb_secure_queue;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
uint64_t cdm_cb_base;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
uint64_t cdm_cb;
/* Only used when feature CDM_USER_MODE_QUEUE is not present. */
uint64_t cdm_ctrl_stream_base;
uint64_t cdm_context_state_base_addr;
/* Only used when BRN 49927 is present. */
uint32_t tpu;
uint32_t cdm_resume_pds1;
@@ -462,11 +513,15 @@ struct rogue_fwif_cmd_compute {
struct rogue_fwif_cdm_regs ALIGN_ATTR(8) regs;
uint32_t ALIGN_ATTR(8) flags;
/* FIXME: HIGH: RGX_FEATURE_GPU_MULTICORE_SUPPORT changes the structure's
* layout. Commenting out for now as it's not supported by 4.V.2.51.
*/
/* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */
uint32_t num_temp_regions;
/* Only used when feature CDM_USER_MODE_QUEUE present. */
uint32_t stream_start_offset;
/* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */
/* uint32_t execute_count; */
/* Only used when feature GPU_MULTICORE_SUPPORT present. */
uint32_t execute_count;
};
static_assert(
src/imagination/vulkan/winsys/pvrsrvkm/fw-api/pvr_rogue_fwif_shared.h
+14 -1
View File
@@ -35,6 +35,8 @@
#define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U
#define ROGUE_NUM_GEOM_CORES 1U
#define ROGUE_NUM_GEOM_CORES_SIZE 2U
/**
* Maximum number of UFOs in a CCB command.
* The number is based on having 32 sync prims (as originally), plus 32 sync
@@ -63,6 +65,7 @@ struct rogue_fwif_dev_addr {
struct rogue_fwif_dma_addr {
uint64_t ALIGN_ATTR(8) dev_vaddr;
struct rogue_fwif_dev_addr fw_addr;
uint32_t padding;
} ALIGN_ATTR(8);
/**
@@ -180,6 +183,16 @@ struct rogue_fwif_cccb_ctl {
/** Offset wrapping mask, total capacity in bytes of the CCB-1. */
uint32_t wrap_mask;
/* Only used if SUPPORT_AGP is present. */
uint32_t read_offset2;
/* Only used if SUPPORT_AGP4 is present. */
uint32_t read_offset3;
/* Only used if SUPPORT_AGP4 is present. */
uint32_t read_offset4;
uint32_t padding;
} ALIGN_ATTR(8);
#define ROGUE_FW_LOCAL_FREELIST 0U
@@ -242,7 +255,7 @@ struct rogue_fwif_cdm_regs_cswitch {
struct rogue_fwif_static_rendercontext_state {
/** Geom registers for ctx switch. */
struct rogue_fwif_ta_regs_cswitch
ALIGN_ATTR(8) ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES];
ALIGN_ATTR(8) ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES_SIZE];
};
#define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \
src/imagination/vulkan/winsys/pvrsrvkm/pvr_srv_job_compute.c
+1 -1
View File
@@ -150,7 +150,7 @@ static void pvr_srv_compute_cmd_init(
fw_regs->cdm_item = submit_info->regs.cdm_item;
fw_regs->compute_cluster = submit_info->regs.compute_cluster;
fw_regs->cdm_ctrl_stream_base = submit_info->regs.cdm_ctrl_stream_base;
fw_regs->cdm_contex_state_base_addr =
fw_regs->cdm_context_state_base_addr =
submit_info->regs.cdm_ctx_state_base_addr;
fw_regs->tpu = submit_info->regs.tpu;
fw_regs->cdm_resume_pds1 = submit_info->regs.cdm_resume_pds1;
src/imagination/vulkan/winsys/pvrsrvkm/pvr_srv_job_render.c
-2
View File
@@ -295,8 +295,6 @@ static void pvr_srv_render_ctx_fw_static_state_init(
struct rogue_fwif_ta_regs_cswitch *regs =
&static_state->ctx_switch_geom_regs[0];
STATIC_ASSERT(ARRAY_SIZE(static_state->ctx_switch_geom_regs) == 1);
memset(static_state, 0, sizeof(*static_state));
regs->vdm_context_state_base_addr = ws_static_state->vdm_ctx_state_base_addr;