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intel/compiler: Don't use half float param for sample_b

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Looks like some of the tests uses the bias which does not fit into half
float parameter, so it's better to use float param for sample_b.

If we have cube arrays, we anyway combine BIAS and array index properly
so we don't have to worry about the first parameter.

This fixes: GTF-GL46.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_clamp_m_g_M

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29533>
This commit is contained in:
Sagar Ghuge
2024-06-02 19:12:14 -07:00
committed by Marge Bot
parent d8c2930da0
commit edcad250ed
4 changed files with 3 additions and 16 deletions
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src/intel/compiler/brw_fs_nir.cpp
-4
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@@ -8253,7 +8253,6 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
ASSERTED bool got_lod = false;
ASSERTED bool got_bias = false;
bool pack_lod_and_array_index = false;
bool pack_lod_bias_and_offset = false;
uint32_t header_bits = 0;
for (unsigned i = 0; i < instr->num_srcs; i++) {
@@ -8402,7 +8401,6 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
case nir_tex_src_backend1:
assert(!got_lod && !got_bias);
got_lod = true;
pack_lod_and_array_index = true;
assert(instr->op == nir_texop_txl || instr->op == nir_texop_txb);
srcs[TEX_LOGICAL_SRC_LOD] =
retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_TYPE_F);
@@ -8536,8 +8534,6 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
inst->offset = header_bits;
inst->has_packed_lod_ai_src = pack_lod_and_array_index;
const unsigned dest_size = nir_tex_instr_dest_size(instr);
unsigned read_size = dest_size;
if (instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) {