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zink: use zink_shader::info instead of zink_shader::nir::info

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no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22266>
This commit is contained in:
Mike Blumenkrantz
2023-03-28 18:42:44 -04:00
committed by Marge Bot
parent b33d5d1a98
commit edc804e50f
7 changed files with 58 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/zink/zink_compiler.c
+13 -13
View File
@@ -1842,7 +1842,7 @@ update_so_info(struct zink_shader *zs, nir_shader *nir, const struct pipe_stream
unsigned slot = reverse_map[output->register_index];
/* always set stride to be used during draw */
zs->sinfo.so_info.stride[output->output_buffer] = so_info->stride[output->output_buffer];
if (zs->nir->info.stage != MESA_SHADER_GEOMETRY || util_bitcount(zs->nir->info.gs.active_stream_mask) == 1) {
if (zs->info.stage != MESA_SHADER_GEOMETRY || util_bitcount(zs->info.gs.active_stream_mask) == 1) {
nir_variable *var = NULL;
unsigned so_slot;
while (!var)
@@ -3161,7 +3161,7 @@ zink_shader_spirv_compile(struct zink_screen *screen, struct zink_shader *zs, st
VkSpecializationInfo sinfo = {0};
VkSpecializationMapEntry me[3];
uint32_t size[3] = {1,1,1};
if (!zs->nir->info.workgroup_size[0]) {
if (!zs->info.workgroup_size[0]) {
sinfo.mapEntryCount = 3;
sinfo.pMapEntries = &me[0];
sinfo.dataSize = sizeof(uint32_t) * 3;
@@ -3176,7 +3176,7 @@ zink_shader_spirv_compile(struct zink_screen *screen, struct zink_shader *zs, st
}
nir_shader *nir = spirv_to_nir(spirv->words, spirv->num_words,
spec_entries, num_spec_entries,
clamp_stage(zs->nir), "main", &spirv_options, &screen->nir_options);
clamp_stage(&zs->info), "main", &spirv_options, &screen->nir_options);
assert(nir);
ralloc_free(nir);
free(spec_entries);
@@ -3407,7 +3407,7 @@ compile_module(struct zink_screen *screen, struct zink_shader *zs, nir_shader *n
mod = zink_shader_spirv_compile(screen, zs, spirv);
/* TODO: determine if there's any reason to cache spirv output? */
if (zs->nir->info.stage == MESA_SHADER_TESS_CTRL && zs->non_fs.is_generated)
if (zs->info.stage == MESA_SHADER_TESS_CTRL && zs->non_fs.is_generated)
zs->spirv = spirv;
else
ralloc_free(spirv);
@@ -3437,7 +3437,7 @@ zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs,
/* TODO: use a separate mem ctx here for ralloc */
if (!screen->optimal_keys) {
switch (zs->nir->info.stage) {
switch (zs->info.stage) {
case MESA_SHADER_VERTEX: {
uint32_t decomposed_attrs = 0, decomposed_attrs_without_w = 0;
const struct zink_vs_key *vs_key = zink_vs_key(key);
@@ -3490,7 +3490,7 @@ zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs,
}
}
switch (zs->nir->info.stage) {
switch (zs->info.stage) {
case MESA_SHADER_VERTEX:
case MESA_SHADER_TESS_EVAL:
case MESA_SHADER_GEOMETRY:
@@ -4737,7 +4737,7 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
subgroup_options.ballot_bit_size = 32;
subgroup_options.ballot_components = 4;
subgroup_options.lower_subgroup_masks = true;
if (!(screen->info.subgroup.supportedStages & mesa_to_vk_shader_stage(clamp_stage(nir)))) {
if (!(screen->info.subgroup.supportedStages & mesa_to_vk_shader_stage(clamp_stage(&nir->info)))) {
subgroup_options.subgroup_size = 1;
subgroup_options.lower_vote_trivial = true;
}
@@ -4815,7 +4815,7 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
ztype = ZINK_DESCRIPTOR_TYPE_UBO;
/* buffer 0 is a push descriptor */
var->data.descriptor_set = !!var->data.driver_location;
var->data.binding = !var->data.driver_location ? clamp_stage(nir) :
var->data.binding = !var->data.driver_location ? clamp_stage(&nir->info) :
zink_binding(nir->info.stage,
VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER,
var->data.driver_location,
@@ -4954,10 +4954,10 @@ zink_shader_finalize(struct pipe_screen *pscreen, void *nirptr)
void
zink_shader_free(struct zink_screen *screen, struct zink_shader *shader)
{
assert(shader->nir->info.stage != MESA_SHADER_COMPUTE);
assert(shader->info.stage != MESA_SHADER_COMPUTE);
set_foreach(shader->programs, entry) {
struct zink_gfx_program *prog = (void*)entry->key;
gl_shader_stage stage = shader->nir->info.stage;
gl_shader_stage stage = shader->info.stage;
assert(stage < ZINK_GFX_SHADER_COUNT);
if (!prog->base.removed && prog->stages_present == prog->stages_remaining &&
(stage == MESA_SHADER_FRAGMENT || !shader->non_fs.is_generated)) {
@@ -5015,7 +5015,7 @@ zink_shader_free(struct zink_screen *screen, struct zink_shader *shader)
}
zink_gfx_program_reference(screen, &prog, NULL);
}
if (shader->nir->info.stage == MESA_SHADER_TESS_EVAL &&
if (shader->info.stage == MESA_SHADER_TESS_EVAL &&
shader->non_fs.generated_tcs) {
/* automatically destroy generated tcs shaders when tes is destroyed */
zink_shader_free(screen, shader->non_fs.generated_tcs);
@@ -5023,7 +5023,7 @@ zink_shader_free(struct zink_screen *screen, struct zink_shader *shader)
}
for (unsigned int i = 0; i < ARRAY_SIZE(shader->non_fs.generated_gs); i++) {
for (int j = 0; j < ARRAY_SIZE(shader->non_fs.generated_gs[0]); j++) {
if (shader->nir->info.stage != MESA_SHADER_FRAGMENT &&
if (shader->info.stage != MESA_SHADER_FRAGMENT &&
shader->non_fs.generated_gs[i][j]) {
/* automatically destroy generated gs shaders when owner is destroyed */
zink_shader_free(screen, shader->non_fs.generated_gs[i][j]);
@@ -5049,7 +5049,7 @@ zink_shader_free(struct zink_screen *screen, struct zink_shader *shader)
VkShaderModule
zink_shader_tcs_compile(struct zink_screen *screen, struct zink_shader *zs, unsigned patch_vertices)
{
assert(zs->nir->info.stage == MESA_SHADER_TESS_CTRL);
assert(zs->info.stage == MESA_SHADER_TESS_CTRL);
/* shortcut all the nir passes since we just have to change this one word */
zs->spirv->words[zs->spirv->tcs_vertices_out_word] = patch_vertices;
return zink_shader_spirv_compile(screen, zs, NULL);
src/gallium/drivers/zink/zink_compiler.h
+2 -2
View File
@@ -43,9 +43,9 @@ struct spirv_shader;
struct tgsi_token;
static inline gl_shader_stage
clamp_stage(nir_shader *nir)
clamp_stage(const shader_info *info)
{
return nir->info.stage == MESA_SHADER_KERNEL ? MESA_SHADER_COMPUTE : nir->info.stage;
return info->stage == MESA_SHADER_KERNEL ? MESA_SHADER_COMPUTE : info->stage;
}
const void *
src/gallium/drivers/zink/zink_context.c
+4 -4
View File
@@ -2485,7 +2485,7 @@ zink_update_fbfetch(struct zink_context *ctx)
{
const bool had_fbfetch = ctx->di.fbfetch.imageLayout == VK_IMAGE_LAYOUT_GENERAL;
if (!ctx->gfx_stages[MESA_SHADER_FRAGMENT] ||
!ctx->gfx_stages[MESA_SHADER_FRAGMENT]->nir->info.fs.uses_fbfetch_output) {
!ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info.fs.uses_fbfetch_output) {
if (!had_fbfetch)
return;
ctx->rp_changed = true;
@@ -4757,9 +4757,9 @@ static void
zink_tc_parse_fs(void *state, struct tc_renderpass_info *info)
{
struct zink_shader *zs = state;
info->zsbuf_write_fs |= zs->nir->info.outputs_written & (BITFIELD64_BIT(FRAG_RESULT_DEPTH) | BITFIELD64_BIT(FRAG_RESULT_STENCIL));
info->zsbuf_write_fs |= zs->info.outputs_written & (BITFIELD64_BIT(FRAG_RESULT_DEPTH) | BITFIELD64_BIT(FRAG_RESULT_STENCIL));
/* TODO: if >1 fbfetch attachment is ever supported */
info->cbuf_fbfetch |= zs->nir->info.fs.uses_fbfetch_output ? BITFIELD_BIT(0) : 0;
info->cbuf_fbfetch |= zs->info.fs.uses_fbfetch_output ? BITFIELD_BIT(0) : 0;
}
void
@@ -5127,7 +5127,7 @@ add_implicit_feedback_loop(struct zink_context *ctx, struct zink_resource *res)
/* in-range VkPipelineStageFlagBits can be converted to VkShaderStageFlags with a bitshift */
gl_shader_stage stage = vk_to_mesa_shader_stage((VkShaderStageFlagBits)(vkstagebit >> 3));
/* check shader texture usage against resource's sampler binds */
if ((ctx->gfx_stages[stage] && (res->sampler_binds[stage] & ctx->gfx_stages[stage]->nir->info.textures_used[0])))
if ((ctx->gfx_stages[stage] && (res->sampler_binds[stage] & ctx->gfx_stages[stage]->info.textures_used[0])))
is_feedback = true;
}
if (!is_feedback)
src/gallium/drivers/zink/zink_descriptors.c
+8 -8
View File
@@ -313,7 +313,7 @@ init_db_template_entry(struct zink_screen *screen, struct zink_shader *shader, e
unsigned idx, struct zink_descriptor_template *entry, unsigned *entry_idx)
{
int index = shader->bindings[type][idx].index;
gl_shader_stage stage = shader->nir->info.stage;
gl_shader_stage stage = shader->info.stage;
entry->count = shader->bindings[type][idx].size;
switch (shader->bindings[type][idx].type) {
@@ -368,7 +368,7 @@ init_template_entry(struct zink_shader *shader, enum zink_descriptor_type type,
unsigned idx, VkDescriptorUpdateTemplateEntry *entry, unsigned *entry_idx)
{
int index = shader->bindings[type][idx].index;
gl_shader_stage stage = clamp_stage(shader->nir);
gl_shader_stage stage = clamp_stage(&shader->info);
entry->dstArrayElement = 0;
entry->dstBinding = shader->bindings[type][idx].binding;
entry->descriptorCount = shader->bindings[type][idx].size;
@@ -485,7 +485,7 @@ zink_descriptor_program_init(struct zink_context *ctx, struct zink_program *pg)
else
stages = ((struct zink_gfx_program*)pg)->shaders;
if (!pg->is_compute && stages[MESA_SHADER_FRAGMENT]->nir->info.fs.uses_fbfetch_output) {
if (!pg->is_compute && stages[MESA_SHADER_FRAGMENT]->info.fs.uses_fbfetch_output) {
push_count = 1;
pg->dd.fbfetch = true;
}
@@ -515,7 +515,7 @@ zink_descriptor_program_init(struct zink_context *ctx, struct zink_program *pg)
if (!shader)
continue;
gl_shader_stage stage = clamp_stage(shader->nir);
gl_shader_stage stage = clamp_stage(&shader->info);
VkShaderStageFlagBits stage_flags = mesa_to_vk_shader_stage(stage);
/* uniform ubos handled in push */
if (shader->has_uniforms) {
@@ -580,7 +580,7 @@ zink_descriptor_program_init(struct zink_context *ctx, struct zink_program *pg)
/* some sets can have multiple descriptor types: ensure the size arrays for these types are contiguous for creating the pool key */
VkDescriptorPoolSize *sz = &sizes[idx];
VkDescriptorPoolSize sz2[5];
if (screen->compact_descriptors || (pg->is_compute && stages[0]->nir->info.stage == MESA_SHADER_KERNEL)) {
if (screen->compact_descriptors || (pg->is_compute && stages[0]->info.stage == MESA_SHADER_KERNEL)) {
unsigned found = 0;
while (found < num_type_sizes[desc_type]) {
if (sz->descriptorCount) {
@@ -686,7 +686,7 @@ zink_descriptor_shader_init(struct zink_screen *screen, struct zink_shader *shad
{
VkDescriptorSetLayoutBinding bindings[ZINK_DESCRIPTOR_BASE_TYPES * ZINK_MAX_DESCRIPTORS_PER_TYPE];
unsigned num_bindings = 0;
VkShaderStageFlagBits stage_flags = mesa_to_vk_shader_stage(shader->nir->info.stage);
VkShaderStageFlagBits stage_flags = mesa_to_vk_shader_stage(shader->info.stage);
unsigned desc_set_size = shader->has_uniforms;
for (unsigned i = 0; i < ZINK_DESCRIPTOR_BASE_TYPES; i++)
@@ -703,7 +703,7 @@ zink_descriptor_shader_init(struct zink_screen *screen, struct zink_shader *shad
binding->pImmutableSamplers = NULL;
struct zink_descriptor_template *entry = &shader->precompile.db_template[num_bindings];
entry->count = 1;
entry->offset = offsetof(struct zink_context, di.db.ubos[shader->nir->info.stage][0]);
entry->offset = offsetof(struct zink_context, di.db.ubos[shader->info.stage][0]);
entry->stride = sizeof(VkDescriptorAddressInfoEXT);
entry->db_size = screen->info.db_props.robustUniformBufferDescriptorSize;
num_bindings++;
@@ -746,7 +746,7 @@ zink_descriptor_shader_init(struct zink_screen *screen, struct zink_shader *shad
if (shader->bindless)
num_dsl = screen->compact_descriptors ? ZINK_DESCRIPTOR_ALL_TYPES - ZINK_DESCRIPTOR_COMPACT : ZINK_DESCRIPTOR_ALL_TYPES;
if (num_bindings || shader->bindless) {
dsl[shader->nir->info.stage == MESA_SHADER_FRAGMENT] = shader->precompile.dsl;
dsl[shader->info.stage == MESA_SHADER_FRAGMENT] = shader->precompile.dsl;
if (shader->bindless)
dsl[screen->desc_set_id[ZINK_DESCRIPTOR_BINDLESS]] = screen->bindless_layout;
}
src/gallium/drivers/zink/zink_program.c
+29 -29
View File
@@ -112,12 +112,12 @@ gather_shader_module_info(struct zink_context *ctx, struct zink_screen *screen,
bool has_nonseamless, //is nonseamless ext present?
unsigned *inline_size, unsigned *nonseamless_size)
{
gl_shader_stage stage = zs->nir->info.stage;
gl_shader_stage stage = zs->info.stage;
struct zink_shader_key *key = &state->shader_keys.key[stage];
if (has_inline && ctx && zs->nir->info.num_inlinable_uniforms &&
if (has_inline && ctx && zs->info.num_inlinable_uniforms &&
ctx->inlinable_uniforms_valid_mask & BITFIELD64_BIT(stage)) {
if (zs->can_inline && (screen->is_cpu || prog->inlined_variant_count[stage] < ZINK_MAX_INLINED_VARIANTS))
*inline_size = zs->nir->info.num_inlinable_uniforms;
*inline_size = zs->info.num_inlinable_uniforms;
else
key->inline_uniforms = false;
}
@@ -590,7 +590,7 @@ void
zink_gfx_program_update(struct zink_context *ctx)
{
if (ctx->last_vertex_stage_dirty) {
gl_shader_stage pstage = ctx->last_vertex_stage->nir->info.stage;
gl_shader_stage pstage = ctx->last_vertex_stage->info.stage;
ctx->dirty_gfx_stages |= BITFIELD_BIT(pstage);
memcpy(&ctx->gfx_pipeline_state.shader_keys.key[pstage].key.vs_base,
&ctx->gfx_pipeline_state.shader_keys.last_vertex.key.vs_base,
@@ -661,7 +661,7 @@ update_gfx_program_optimal(struct zink_context *ctx, struct zink_gfx_program *pr
const union zink_shader_key_optimal *optimal_key = (union zink_shader_key_optimal*)&prog->last_variant_hash;
if (ctx->gfx_pipeline_state.shader_keys_optimal.key.vs_bits != optimal_key->vs_bits) {
assert(!prog->is_separable);
bool changed = update_gfx_shader_module_optimal(ctx, prog, ctx->last_vertex_stage->nir->info.stage);
bool changed = update_gfx_shader_module_optimal(ctx, prog, ctx->last_vertex_stage->info.stage);
ctx->gfx_pipeline_state.modules_changed |= changed;
}
const bool shadow_needs_shader_swizzle = optimal_key->fs.shadow_needs_shader_swizzle && (ctx->dirty_gfx_stages & BITFIELD_BIT(MESA_SHADER_FRAGMENT));
@@ -799,10 +799,10 @@ update_cs_shader_module(struct zink_context *ctx, struct zink_compute_program *c
ASSERTED bool check_robustness = screen->driver_workarounds.lower_robustImageAccess2 && (ctx->flags & PIPE_CONTEXT_ROBUST_BUFFER_ACCESS);
assert(zink_cs_key(key)->robust_access == check_robustness);
if (ctx && zs->nir->info.num_inlinable_uniforms &&
if (ctx && zs->info.num_inlinable_uniforms &&
ctx->inlinable_uniforms_valid_mask & BITFIELD64_BIT(MESA_SHADER_COMPUTE)) {
if (screen->is_cpu || comp->inlined_variant_count < ZINK_MAX_INLINED_VARIANTS)
inline_size = zs->nir->info.num_inlinable_uniforms;
inline_size = zs->info.num_inlinable_uniforms;
else
key->inline_uniforms = false;
}
@@ -1069,7 +1069,7 @@ zink_create_gfx_program(struct zink_context *ctx,
_mesa_hash_table_init(&prog->pipelines[r][i], prog, NULL, zink_get_gfx_pipeline_eq_func(screen, prog));
/* only need first 3/4 for point/line/tri/patch */
if (screen->info.have_EXT_extended_dynamic_state &&
i == (prog->last_vertex_stage->nir->info.stage == MESA_SHADER_TESS_EVAL ? 4 : 3))
i == (prog->last_vertex_stage->info.stage == MESA_SHADER_TESS_EVAL ? 4 : 3))
break;
}
}
@@ -1163,7 +1163,7 @@ create_gfx_program_separable(struct zink_context *ctx, struct zink_shader **stag
_mesa_hash_table_init(&prog->pipelines[r][i], prog, NULL, zink_get_gfx_pipeline_eq_func(screen, prog));
/* only need first 3/4 for point/line/tri/patch */
if (screen->info.have_EXT_extended_dynamic_state &&
i == (prog->last_vertex_stage->nir->info.stage == MESA_SHADER_TESS_EVAL ? 4 : 3))
i == (prog->last_vertex_stage->info.stage == MESA_SHADER_TESS_EVAL ? 4 : 3))
break;
}
}
@@ -1334,9 +1334,9 @@ zink_program_get_descriptor_usage(struct zink_context *ctx, gl_shader_stage stag
case ZINK_DESCRIPTOR_TYPE_SSBO:
return zs->ssbos_used;
case ZINK_DESCRIPTOR_TYPE_SAMPLER_VIEW:
return BITSET_TEST_RANGE(zs->nir->info.textures_used, 0, PIPE_MAX_SAMPLERS - 1);
return BITSET_TEST_RANGE(zs->info.textures_used, 0, PIPE_MAX_SAMPLERS - 1);
case ZINK_DESCRIPTOR_TYPE_IMAGE:
return BITSET_TEST_RANGE(zs->nir->info.images_used, 0, PIPE_MAX_SAMPLERS - 1);
return BITSET_TEST_RANGE(zs->info.images_used, 0, PIPE_MAX_SAMPLERS - 1);
default:
unreachable("unknown descriptor type!");
}
@@ -1568,7 +1568,7 @@ zink_get_compute_pipeline(struct zink_screen *screen,
static void
bind_gfx_stage(struct zink_context *ctx, gl_shader_stage stage, struct zink_shader *shader)
{
if (shader && shader->nir->info.num_inlinable_uniforms)
if (shader && shader->info.num_inlinable_uniforms)
ctx->shader_has_inlinable_uniforms_mask |= 1 << stage;
else
ctx->shader_has_inlinable_uniforms_mask &= ~(1 << stage);
@@ -1625,7 +1625,7 @@ gs_output_to_reduced_prim_type(struct shader_info *info)
static enum pipe_prim_type
update_rast_prim(struct zink_shader *shader)
{
struct shader_info *info = &shader->nir->info;
struct shader_info *info = &shader->info;
if (info->stage == MESA_SHADER_GEOMETRY)
return gs_output_to_reduced_prim_type(info);
else if (info->stage == MESA_SHADER_TESS_EVAL) {
@@ -1665,14 +1665,14 @@ bind_last_vertex_stage(struct zink_context *ctx, gl_shader_stage stage, struct z
if (prev_shader && stage < MESA_SHADER_GEOMETRY)
unbind_generated_gs(ctx, stage, prev_shader);
gl_shader_stage old = ctx->last_vertex_stage ? ctx->last_vertex_stage->nir->info.stage : MESA_SHADER_STAGES;
gl_shader_stage old = ctx->last_vertex_stage ? ctx->last_vertex_stage->info.stage : MESA_SHADER_STAGES;
if (ctx->gfx_stages[MESA_SHADER_GEOMETRY])
ctx->last_vertex_stage = ctx->gfx_stages[MESA_SHADER_GEOMETRY];
else if (ctx->gfx_stages[MESA_SHADER_TESS_EVAL])
ctx->last_vertex_stage = ctx->gfx_stages[MESA_SHADER_TESS_EVAL];
else
ctx->last_vertex_stage = ctx->gfx_stages[MESA_SHADER_VERTEX];
gl_shader_stage current = ctx->last_vertex_stage ? ctx->last_vertex_stage->nir->info.stage : MESA_SHADER_VERTEX;
gl_shader_stage current = ctx->last_vertex_stage ? ctx->last_vertex_stage->info.stage : MESA_SHADER_VERTEX;
/* update rast_prim */
ctx->gfx_pipeline_state.shader_rast_prim =
@@ -1694,7 +1694,7 @@ bind_last_vertex_stage(struct zink_context *ctx, gl_shader_stage stage, struct z
struct zink_screen *screen = zink_screen(ctx->base.screen);
/* number of enabled viewports is based on whether last vertex stage writes viewport index */
if (ctx->last_vertex_stage) {
if (ctx->last_vertex_stage->nir->info.outputs_written & (VARYING_BIT_VIEWPORT | VARYING_BIT_VIEWPORT_MASK))
if (ctx->last_vertex_stage->info.outputs_written & (VARYING_BIT_VIEWPORT | VARYING_BIT_VIEWPORT_MASK))
ctx->vp_state.num_viewports = MIN2(screen->info.props.limits.maxViewports, PIPE_MAX_VIEWPORTS);
else
ctx->vp_state.num_viewports = 1;
@@ -1723,8 +1723,8 @@ zink_bind_vs_state(struct pipe_context *pctx,
bind_last_vertex_stage(ctx, MESA_SHADER_VERTEX, prev_shader);
if (cso) {
struct zink_shader *zs = cso;
ctx->shader_reads_drawid = BITSET_TEST(zs->nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
ctx->shader_reads_basevertex = BITSET_TEST(zs->nir->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX);
ctx->shader_reads_drawid = BITSET_TEST(zs->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
ctx->shader_reads_basevertex = BITSET_TEST(zs->info.system_values_read, SYSTEM_VALUE_BASE_VERTEX);
} else {
ctx->shader_reads_drawid = false;
ctx->shader_reads_basevertex = false;
@@ -1740,8 +1740,8 @@ zink_update_fs_key_samples(struct zink_context *ctx)
{
if (!ctx->gfx_stages[MESA_SHADER_FRAGMENT])
return;
nir_shader *nir = ctx->gfx_stages[MESA_SHADER_FRAGMENT]->nir;
if (nir->info.outputs_written & (1 << FRAG_RESULT_SAMPLE_MASK)) {
shader_info *info = &ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info;
if (info->outputs_written & (1 << FRAG_RESULT_SAMPLE_MASK)) {
bool samples = zink_get_fs_base_key(ctx)->samples;
if (samples != (ctx->fb_state.samples > 1))
zink_set_fs_base_key(ctx)->samples = ctx->fb_state.samples > 1;
@@ -1766,8 +1766,8 @@ zink_bind_fs_state(struct pipe_context *pctx,
bind_gfx_stage(ctx, MESA_SHADER_FRAGMENT, cso);
ctx->fbfetch_outputs = 0;
if (cso) {
nir_shader *nir = ctx->gfx_stages[MESA_SHADER_FRAGMENT]->nir;
if (nir->info.fs.uses_fbfetch_output) {
shader_info *info = &ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info;
if (info->fs.uses_fbfetch_output) {
nir_foreach_shader_out_variable(var, ctx->gfx_stages[MESA_SHADER_FRAGMENT]->nir) {
if (var->data.fb_fetch_output)
ctx->fbfetch_outputs |= BITFIELD_BIT(var->data.location - FRAG_RESULT_DATA0);
@@ -1775,9 +1775,9 @@ zink_bind_fs_state(struct pipe_context *pctx,
}
zink_update_fs_key_samples(ctx);
if (zink_screen(pctx->screen)->info.have_EXT_rasterization_order_attachment_access) {
if (ctx->gfx_pipeline_state.rast_attachment_order != nir->info.fs.uses_fbfetch_output)
if (ctx->gfx_pipeline_state.rast_attachment_order != info->fs.uses_fbfetch_output)
ctx->gfx_pipeline_state.dirty = true;
ctx->gfx_pipeline_state.rast_attachment_order = nir->info.fs.uses_fbfetch_output;
ctx->gfx_pipeline_state.rast_attachment_order = info->fs.uses_fbfetch_output;
}
zink_set_zs_needs_shader_swizzle_key(ctx, MESA_SHADER_FRAGMENT, false);
if (shadow_mask != ctx->gfx_stages[MESA_SHADER_FRAGMENT]->fs.legacy_shadow_mask &&
@@ -2038,7 +2038,7 @@ precompile_separate_shader_job(void *data, void *gdata, int thread_index)
zs->precompile.mod = zink_shader_compile_separate(screen, zs);
zink_descriptor_shader_init(screen, zs);
VkShaderModule mods[ZINK_GFX_SHADER_COUNT] = {0};
mods[zs->nir->info.stage] = zs->precompile.mod;
mods[zs->info.stage] = zs->precompile.mod;
zs->precompile.gpl = zink_create_gfx_pipeline_separate(screen, mods, zs->precompile.layout);
}
@@ -2053,10 +2053,10 @@ zink_link_gfx_shader(struct pipe_context *pctx, void **shaders)
if (!shaders[MESA_SHADER_VERTEX] || !shaders[MESA_SHADER_FRAGMENT]) {
if (shaders[MESA_SHADER_VERTEX] || shaders[MESA_SHADER_FRAGMENT]) {
struct zink_shader *zs = shaders[MESA_SHADER_VERTEX] ? shaders[MESA_SHADER_VERTEX] : shaders[MESA_SHADER_FRAGMENT];
if (zs->nir->info.separate_shader && !zs->precompile.mod && util_queue_fence_is_signalled(&zs->precompile.fence) &&
if (zs->info.separate_shader && !zs->precompile.mod && util_queue_fence_is_signalled(&zs->precompile.fence) &&
zink_descriptor_mode == ZINK_DESCRIPTOR_MODE_DB &&
/* sample shading can't precompile */
(!shaders[MESA_SHADER_FRAGMENT] || !zs->nir->info.fs.uses_sample_shading))
(!shaders[MESA_SHADER_FRAGMENT] || !zs->info.fs.uses_sample_shading))
util_queue_add_job(&zink_screen(pctx->screen)->cache_get_thread, zs, &zs->precompile.fence, precompile_separate_shader_job, NULL, 0);
}
return;
@@ -2301,10 +2301,10 @@ zink_set_primitive_emulation_keys(struct zink_context *ctx)
zink_rast_prim_for_pipe(ctx->gfx_pipeline_state.rast_prim);
//when using transform feedback primitives must be tessellated
lower_filled_quad |= lower_quad_prim && ctx->gfx_stages[prev_vertex_stage]->nir->info.has_transform_feedback_varyings;
lower_filled_quad |= lower_quad_prim && ctx->gfx_stages[prev_vertex_stage]->info.has_transform_feedback_varyings;
if (!ctx->gfx_stages[MESA_SHADER_GEOMETRY] ||
(ctx->gfx_stages[MESA_SHADER_GEOMETRY]->nir->info.gs.input_primitive != ctx->gfx_pipeline_state.gfx_prim_mode)) {
(ctx->gfx_stages[MESA_SHADER_GEOMETRY]->info.gs.input_primitive != ctx->gfx_pipeline_state.gfx_prim_mode)) {
if (!ctx->gfx_stages[prev_vertex_stage]->non_fs.generated_gs[ctx->gfx_pipeline_state.gfx_prim_mode][zink_prim_type]) {
nir_shader *nir;
src/gallium/drivers/zink/zink_program.h
+1 -1
View File
@@ -411,7 +411,7 @@ zink_can_use_pipeline_libs(const struct zink_context *ctx)
/* this is just terrible */
!zink_get_fs_base_key(ctx)->shadow_needs_shader_swizzle &&
/* TODO: is sample shading even possible to handle with GPL? */
!ctx->gfx_stages[MESA_SHADER_FRAGMENT]->nir->info.fs.uses_sample_shading &&
!ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info.fs.uses_sample_shading &&
!zink_get_fs_base_key(ctx)->fbfetch_ms &&
!ctx->gfx_pipeline_state.force_persample_interp &&
!ctx->gfx_pipeline_state.min_samples &&
src/gallium/drivers/zink/zink_render_pass.c
+1 -1
View File
@@ -370,7 +370,7 @@ zink_init_zs_attachment(struct zink_context *ctx, struct zink_rt_attrib *rt)
!zink_fb_clear_first_needs_explicit(fb_clear) &&
(zink_fb_clear_element(fb_clear, 0)->zs.bits & PIPE_CLEAR_STENCIL);
const uint64_t outputs_written = ctx->gfx_stages[MESA_SHADER_FRAGMENT] ?
ctx->gfx_stages[MESA_SHADER_FRAGMENT]->nir->info.outputs_written : 0;
ctx->gfx_stages[MESA_SHADER_FRAGMENT]->info.outputs_written : 0;
bool needs_write_z = (ctx->dsa_state && ctx->dsa_state->hw_state.depth_write) ||
outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH);
needs_write_z |= transient || rt->clear_color ||