radeon: Update regulary cs processing info from kernel.
This fixes problem that dma buffers were leaking in dri1 mode. Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
This commit is contained in:
committed by
Alex Deucher
parent
8604a896a6
commit
ec1540052b
@@ -235,8 +235,9 @@ static int legacy_wait_pending(struct radeon_bo *bo)
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return 0;
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}
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static void legacy_track_pending(struct bo_manager_legacy *boml, int debug)
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void legacy_track_pending(struct radeon_bo_manager *bom, int debug)
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{
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struct bo_manager_legacy *boml = (struct bo_manager_legacy*) bom;
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struct bo_legacy *bo_legacy;
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struct bo_legacy *next;
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@@ -244,8 +245,8 @@ static void legacy_track_pending(struct bo_manager_legacy *boml, int debug)
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bo_legacy = boml->pending_bos.pnext;
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while (bo_legacy) {
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if (debug)
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fprintf(stderr,"pending %p %d %d %d\n", bo_legacy, bo_legacy->base.size,
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boml->current_age, bo_legacy->pending);
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fprintf(stderr,"pending %p %d %d %d\n", bo_legacy, bo_legacy->base.size,
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boml->current_age, bo_legacy->pending);
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next = bo_legacy->pnext;
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if (legacy_is_pending(&(bo_legacy->base))) {
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}
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@@ -444,7 +445,7 @@ static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
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if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT)
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{
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retry:
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legacy_track_pending(boml, 0);
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legacy_track_pending(&boml->base, 0);
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/* dma buffers */
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r = bo_dma_alloc(&(bo_legacy->base));
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@@ -580,7 +581,7 @@ static int bo_vram_validate(struct radeon_bo *bo,
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if (r) {
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pending_retry = 0;
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while(boml->cpendings && pending_retry++ < 10000) {
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legacy_track_pending(boml, 0);
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legacy_track_pending(&boml->base, 0);
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retry_count++;
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if (retry_count > 2) {
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free(bo_legacy->tobj);
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@@ -706,7 +707,7 @@ int radeon_bo_legacy_validate(struct radeon_bo *bo,
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r = bo_vram_validate(bo, soffset, eoffset);
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if (r) {
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legacy_track_pending(boml, 0);
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legacy_track_pending(&boml->base, 0);
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legacy_kick_all_buffers(boml);
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retries++;
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if (retries == 2) {
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@@ -45,5 +45,6 @@ unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo);
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struct radeon_bo *radeon_legacy_bo_alloc_fake(struct radeon_bo_manager *bom,
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int size,
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uint32_t offset);
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void legacy_track_pending(struct radeon_bo_manager *bom, int debug);
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#endif
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@@ -326,6 +326,10 @@ void radeonReleaseDmaRegions(radeonContextPtr rmesa)
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__FUNCTION__, free, wait, reserved, rmesa->dma.minimum_size);
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}
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if (!rmesa->radeonScreen->driScreen->dri2.enabled) {
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/* request updated cs processing information from kernel */
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legacy_track_pending(rmesa->radeonScreen->bom, 0);
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}
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/* move waiting bos to free list.
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wait list provides gpu time to handle data before reuse */
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foreach_s(dma_bo, temp, &rmesa->dma.wait) {
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