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amd: update addrlib

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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák
2019-06-14 17:55:38 -04:00
parent d15cc1f55a
commit eba932ea43
28 changed files with 742 additions and 567 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/addrlib/inc/addrinterface.h
+9 -3
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -307,7 +307,8 @@ typedef union _ADDR_CREATE_FLAGS
UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
UINT_32 reserved : 25; ///< Reserved bits for future use
UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility
UINT_32 reserved : 24; ///< Reserved bits for future use
};
UINT_32 value;
@@ -2879,6 +2880,9 @@ typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
UINT_32 unalignedWidth; ///< Color surface original width
UINT_32 unalignedHeight; ///< Color surface original height
UINT_32 numSlices; ///< Number of slices of color buffer
UINT_32 numMipLevels; ///< Number of mip levels
UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
/// it should be number of mip levels
} ADDR2_COMPUTE_CMASK_INFO_INPUT;
/**
@@ -2904,7 +2908,9 @@ typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
UINT_32 metaBlkWidth; ///< Meta block width
UINT_32 metaBlkHeight; ///< Meta block height
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information
} ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
/**
src/amd/addrlib/inc/addrtypes.h
+18 -18
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -567,23 +567,23 @@ typedef enum _AddrHtileBlockSize
*/
typedef enum _AddrPipeCfg
{
ADDR_PIPECFG_INVALID = 0,
ADDR_PIPECFG_P2 = 1, /// 2 pipes,
ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes,
ADDR_PIPECFG_P4_16x16 = 6,
ADDR_PIPECFG_P4_16x32 = 7,
ADDR_PIPECFG_P4_32x32 = 8,
ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes
ADDR_PIPECFG_P8_16x32_8x16 = 10,
ADDR_PIPECFG_P8_32x32_8x16 = 11,
ADDR_PIPECFG_P8_16x32_16x16 = 12,
ADDR_PIPECFG_P8_32x32_16x16 = 13,
ADDR_PIPECFG_P8_32x32_16x32 = 14,
ADDR_PIPECFG_P8_32x64_32x32 = 15,
ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
ADDR_PIPECFG_P16_32x32_16x16 = 18,
ADDR_PIPECFG_RESERVED = 19, /// reserved for internal use
ADDR_PIPECFG_MAX = 20,
ADDR_PIPECFG_INVALID = 0,
ADDR_PIPECFG_P2 = 1, /// 2 pipes,
ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes,
ADDR_PIPECFG_P4_16x16 = 6,
ADDR_PIPECFG_P4_16x32 = 7,
ADDR_PIPECFG_P4_32x32 = 8,
ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes
ADDR_PIPECFG_P8_16x32_8x16 = 10,
ADDR_PIPECFG_P8_32x32_8x16 = 11,
ADDR_PIPECFG_P8_16x32_16x16 = 12,
ADDR_PIPECFG_P8_32x32_16x16 = 13,
ADDR_PIPECFG_P8_32x32_16x32 = 14,
ADDR_PIPECFG_P8_32x64_32x32 = 15,
ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes
ADDR_PIPECFG_P16_32x32_16x16 = 18,
ADDR_PIPECFG_UNUSED = 19,
ADDR_PIPECFG_MAX = 20,
} AddrPipeCfg;
/**
src/amd/addrlib/src/addrinterface.cpp
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/amdgpu_asic_addr.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2017-2018 Advanced Micro Devices, Inc.
* Copyright © 2017-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/chip/gfx9/gfx9_gb_reg.h
+1 -1
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@@ -2,7 +2,7 @@
#define __GFX9_GB_REG_H__
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/chip/r800/si_gb_reg.h
+1 -1
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@@ -2,7 +2,7 @@
#define __SI_GB_REG_H__
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/addrcommon.h
+15 -6
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -36,10 +36,6 @@
#include "addrinterface.h"
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#if !defined(DEBUG)
#ifdef NDEBUG
#define DEBUG 0
@@ -48,6 +44,14 @@
#endif
#endif
// ADDR_LNX_KERNEL_BUILD is for internal build
// Moved from addrinterface.h so __KERNEL__ is not needed any more
#if !defined(__APPLE__) || defined(HAVE_TSERVER)
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#endif
////////////////////////////////////////////////////////////////////////////////////////////////////
// Platform specific debug break defines
////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -152,7 +156,11 @@
#endif // DEBUG
////////////////////////////////////////////////////////////////////////////////////////////////////
#if defined(static_assert)
#define ADDR_C_ASSERT(__e) static_assert(__e, "")
#else
#define ADDR_C_ASSERT(__e) typedef char __ADDR_C_ASSERT__[(__e) ? 1 : -1]
#endif
namespace Addr
{
@@ -260,7 +268,8 @@ union ConfigFlags
UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
UINT_32 disableLinearOpt : 1; ///< Disallow tile modes to be optimized to linear
UINT_32 use32bppFor422Fmt : 1; ///< View 422 formats as 32 bits per pixel element
UINT_32 reserved : 21; ///< Reserved bits for future use
UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility
UINT_32 reserved : 20; ///< Reserved bits for future use
};
UINT_32 value;
src/amd/addrlib/src/core/addrelemlib.cpp
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/addrelemlib.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/addrlib.cpp
+2 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -246,6 +246,7 @@ ADDR_E_RETURNCODE Lib::Create(
pLib->m_configFlags.checkLast2DLevel = pCreateIn->createFlags.checkLast2DLevel;
pLib->m_configFlags.useHtileSliceAlign = pCreateIn->createFlags.useHtileSliceAlign;
pLib->m_configFlags.allowLargeThickTile = pCreateIn->createFlags.allowLargeThickTile;
pLib->m_configFlags.forceDccAndTcCompat = pCreateIn->createFlags.forceDccAndTcCompat;
pLib->m_configFlags.disableLinearOpt = FALSE;
pLib->SetChipFamily(pCreateIn->chipFamily, pCreateIn->chipRevision);
src/amd/addrlib/src/core/addrlib.h
+1 -2
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -409,7 +409,6 @@ private:
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
Lib* Gfx9HwlInit (const Client* pClient);
} // Addr
#endif
src/amd/addrlib/src/core/addrlib1.cpp
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/addrlib1.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/addrlib2.cpp
+23 -25
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -63,7 +63,17 @@ const Dim3d Lib::Block1K_3d[] = {{16, 8, 8}, {8, 8, 8}, {8, 8, 4}, {8, 4, 4}, {
*/
Lib::Lib()
:
Addr::Lib()
Addr::Lib(),
m_se(0),
m_rbPerSe(0),
m_maxCompFrag(0),
m_banksLog2(0),
m_pipesLog2(0),
m_seLog2(0),
m_rbPerSeLog2(0),
m_maxCompFragLog2(0),
m_pipeInterleaveLog2(0),
m_blockVarSizeLog2(0)
{
}
@@ -78,7 +88,17 @@ Lib::Lib()
*/
Lib::Lib(const Client* pClient)
:
Addr::Lib(pClient)
Addr::Lib(pClient),
m_se(0),
m_rbPerSe(0),
m_maxCompFrag(0),
m_banksLog2(0),
m_pipesLog2(0),
m_seLog2(0),
m_rbPerSeLog2(0),
m_maxCompFragLog2(0),
m_pipeInterleaveLog2(0),
m_blockVarSizeLog2(0)
{
}
@@ -1692,28 +1712,6 @@ UINT_32 Lib::GetPipeXorBits(
return pipeBits;
}
/**
************************************************************************************************************************
* Lib::GetBankXorBits
*
* @brief
* Internal function to get bits number for pipe/se xor operation
*
* @return
* ADDR_E_RETURNCODE
************************************************************************************************************************
*/
UINT_32 Lib::GetBankXorBits(
UINT_32 macroBlockBits) const
{
UINT_32 pipeBits = GetPipeXorBits(macroBlockBits);
// Bank xor bits
UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2);
return bankBits;
}
/**
************************************************************************************************************************
* Lib::Addr2GetPreferredSurfaceSetting
src/amd/addrlib/src/core/addrlib2.h
+1 -17
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -691,21 +691,6 @@ protected:
UINT_32 blockHeight,
UINT_32 blockDepth) const;
BOOL_32 IsInMipTail(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
Dim3d mipTailDim,
UINT_32 width,
UINT_32 height,
UINT_32 depth) const
{
BOOL_32 inTail = ((width <= mipTailDim.w) &&
(height <= mipTailDim.h) &&
(IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d)));
return inTail;
}
static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType)
{
return ((resourceType == ADDR_RSRC_LOC_LOCAL) ||
@@ -794,7 +779,6 @@ protected:
}
UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const;
UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const;
ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
src/amd/addrlib/src/core/addrobject.cpp
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/addrobject.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/coord.cpp
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/core/coord.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
+587 -465
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File diff suppressed because it is too large Load Diff
src/amd/addrlib/src/gfx9/gfx9addrlib.h
+29 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -615,6 +615,34 @@ private:
return allowedSwSet;
}
BOOL_32 IsInMipTail(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
Dim3d mipTailDim,
UINT_32 width,
UINT_32 height,
UINT_32 depth) const
{
BOOL_32 inTail = ((width <= mipTailDim.w) &&
(height <= mipTailDim.h) &&
(IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d)));
return inTail;
}
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const
{
UINT_32 pipeBits = GetPipeXorBits(macroBlockBits);
// Bank xor bits
UINT_32 bankBits = Min(macroBlockBits - pipeBits - m_pipeInterleaveLog2, m_banksLog2);
return bankBits;
}
Gfx9ChipSettings m_settings;
CoordEq m_cachedMetaEq[MaxCachedMetaEq];
src/amd/addrlib/src/r800/ciaddrlib.cpp
+8 -8
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -210,7 +210,7 @@ ADDR_E_RETURNCODE CiLib::HwlComputeDccInfo(
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (m_settings.isVolcanicIslands && IsMacroTiled(pIn->tileMode))
if (SupportDccAndTcCompatibility() && IsMacroTiled(pIn->tileMode))
{
UINT_64 dccFastClearSize = pIn->colorSurfSize >> 8;
@@ -294,7 +294,7 @@ ADDR_E_RETURNCODE CiLib::HwlComputeCmaskAddrFromCoord(
{
ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED;
if ((m_settings.isVolcanicIslands == TRUE) &&
if ((SupportDccAndTcCompatibility() == TRUE) &&
(pIn->flags.tcCompatible == TRUE))
{
UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo);
@@ -338,7 +338,7 @@ ADDR_E_RETURNCODE CiLib::HwlComputeHtileAddrFromCoord(
{
ADDR_E_RETURNCODE returnCode = ADDR_NOTSUPPORTED;
if ((m_settings.isVolcanicIslands == TRUE) &&
if ((SupportDccAndTcCompatibility() == TRUE) &&
(pIn->flags.tcCompatible == TRUE))
{
UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo);
@@ -709,7 +709,7 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
if ((pIn->mipLevel > 0) &&
(pOut->tcCompatible == TRUE) &&
(pOut->tileMode != pIn->tileMode) &&
(m_settings.isVolcanicIslands == TRUE))
(SupportDccAndTcCompatibility() == TRUE))
{
pOut->tcCompatible = CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
}
@@ -1303,7 +1303,7 @@ VOID CiLib::HwlSetupTileInfo(
}
// tcCompatible flag is only meaningful for gfx8.
if (m_settings.isVolcanicIslands == FALSE)
if (SupportDccAndTcCompatibility() == FALSE)
{
flags.tcCompatible = FALSE;
}
@@ -2098,7 +2098,7 @@ VOID CiLib::HwlPadDimensions(
UINT_32 heightAlign ///< [in] height alignment
) const
{
if ((m_settings.isVolcanicIslands == TRUE) &&
if ((SupportDccAndTcCompatibility() == TRUE) &&
(flags.dccCompatible == TRUE) &&
(numSamples > 1) &&
(mipLevel == 0) &&
@@ -2208,7 +2208,7 @@ UINT_32 CiLib::HwlComputeMaxMetaBaseAlignments() const
for (UINT_32 i = 0; i < m_noOfMacroEntries; i++)
{
if ((m_settings.isVolcanicIslands) && IsMacroTiled(m_tileTable[i].mode))
if (SupportDccAndTcCompatibility() && IsMacroTiled(m_tileTable[i].mode))
{
maxBank = Max(maxBank, m_macroTileTable[i].banks);
}
src/amd/addrlib/src/r800/ciaddrlib.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -184,6 +184,11 @@ private:
BOOL_32 CheckTcCompatibility(const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
AddrTileType tileType, const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
BOOL_32 SupportDccAndTcCompatibility() const
{
return ((m_settings.isVolcanicIslands == TRUE) || (m_configFlags.forceDccAndTcCompat == TRUE));
}
static const UINT_32 MacroTileTableSize = 16;
static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
static const INT_32 MinDepth2DThinIndex = 0;
src/amd/addrlib/src/r800/egbaddrlib.cpp
+1 -3
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -741,8 +741,6 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMicroTiled(
AdjustPitchAlignment(flags, pPitchAlign);
// Workaround 2 for 1D tiling - There is HW bug for Carrizo,
// where it requires the following alignments for 1D tiling.
if (flags.czDispCompatible && (mipLevel == 0))
{
*pBaseAlign = PowTwoAlign(*pBaseAlign, 4096); //Base address MOD 4096 = 0
src/amd/addrlib/src/r800/egbaddrlib.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/amd/addrlib/src/r800/siaddrlib.cpp
+4 -3
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@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
@@ -1603,8 +1603,9 @@ VOID SiLib::HwlComputeXmaskCoordFromAddr(
{
macroOffset |= (pipebit1<<1);
}
if((pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
(pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_16x16))
if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
(pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_16x16)
)
{
macroOffset |= (pipebit3<<1);
}
src/amd/addrlib/src/r800/siaddrlib.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright © 2007-2018 Advanced Micro Devices, Inc.
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
src/gallium/drivers/radeonsi/si_texture.c
+24
View File
@@ -173,6 +173,11 @@ static void si_copy_from_staging_texture(struct pipe_context *ctx, struct si_tra
return;
}
if (util_format_is_compressed(dst->format)) {
sbox.width = util_format_get_nblocksx(dst->format, sbox.width);
sbox.height = util_format_get_nblocksx(dst->format, sbox.height);
}
sctx->dma_copy(ctx, dst, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
src, 0, &sbox);
@@ -1794,6 +1799,25 @@ static void si_init_temp_resource_from_box(struct pipe_resource *res,
res->usage = flags & SI_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
res->flags = flags;
if (flags & SI_RESOURCE_FLAG_TRANSFER &&
util_format_is_compressed(orig->format)) {
/* Transfer resources are allocated with linear tiling, which is
* not supported for compressed formats.
*/
unsigned blocksize =
util_format_get_blocksize(orig->format);
if (blocksize == 8) {
res->format = PIPE_FORMAT_R16G16B16A16_UINT;
} else {
assert(blocksize == 16);
res->format = PIPE_FORMAT_R32G32B32A32_UINT;
}
res->width0 = util_format_get_nblocksx(orig->format, box->width);
res->height0 = util_format_get_nblocksy(orig->format, box->height);
}
/* We must set the correct texture target and dimensions for a 3D box. */
if (box->depth > 1 && util_max_layer(orig, level) > 0) {
res->target = PIPE_TEXTURE_2D_ARRAY;