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radv: emit more consecutive registers for SQTT on GFX8-9

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This change is only useful to compare the command stream generated by
PM4 in the next commit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
This commit is contained in:
Samuel Pitoiset
2024-05-31 12:10:31 +02:00
committed by Marge Bot
parent a373ba92c3
commit ea8f29b4a7
1 changed files with 11 additions and 15 deletions
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src/amd/vulkan/radv_sqtt.c
+11 -15
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@@ -92,10 +92,6 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367A0_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK,
S_0367B4_WTYPE_INCLUDE(shader_mask) | S_0367B4_SA_SEL(0) |
S_0367B4_WGP_SEL(active_cu / 2) | S_0367B4_SIMD_SEL(0));
uint32_t sqtt_token_mask = S_0367B8_REG_INCLUDE(V_0367B8_REG_INCLUDE_SQDEC | V_0367B8_REG_INCLUDE_SHDEC |
V_0367B8_REG_INCLUDE_GFXUDEC | V_0367B8_REG_INCLUDE_COMP |
V_0367B8_REG_INCLUDE_CONTEXT | V_0367B8_REG_INCLUDE_CONFIG);
@@ -111,7 +107,10 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
}
sqtt_token_mask |= S_0367B8_TOKEN_EXCLUDE_GFX11(token_exclude) | S_0367B8_BOP_EVENTS_TOKEN_INCLUDE_GFX11(1);
radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B8_SQ_THREAD_TRACE_TOKEN_MASK, sqtt_token_mask);
radeon_set_uconfig_perfctr_reg_seq(gfx_level, qf, cs, R_0367B4_SQ_THREAD_TRACE_MASK, 2);
radeon_emit(cs, S_0367B4_WTYPE_INCLUDE(shader_mask) | S_0367B4_SA_SEL(0) | S_0367B4_WGP_SEL(active_cu / 2) |
S_0367B4_SIMD_SEL(0));
radeon_emit(cs, sqtt_token_mask);
/* Should be emitted last (it enables thread traces). */
radeon_set_uconfig_perfctr_reg(gfx_level, qf, cs, R_0367B0_SQ_THREAD_TRACE_CTRL,
@@ -152,9 +151,9 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
/* Order seems important for the following 4 registers. */
radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2, S_030CDC_ADDR_HI(shifted_va >> 32));
radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE, S_030CC4_SIZE(shifted_size));
radeon_set_uconfig_reg_seq(cs, R_030CC0_SQ_THREAD_TRACE_BASE, 2);
radeon_emit(cs, shifted_va);
radeon_emit(cs, S_030CC4_SIZE(shifted_size));
radeon_set_uconfig_reg(cs, R_030CD4_SQ_THREAD_TRACE_CTRL, S_030CD4_RESET_BUFFER(1));
@@ -166,15 +165,12 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
sqtt_mask |= S_030CC8_RANDOM_SEED(0xffff);
}
radeon_set_uconfig_reg(cs, R_030CC8_SQ_THREAD_TRACE_MASK, sqtt_mask);
radeon_set_uconfig_reg_seq(cs, R_030CC8_SQ_THREAD_TRACE_MASK, 3);
radeon_emit(cs, sqtt_mask);
/* Trace all tokens and registers. */
radeon_set_uconfig_reg(cs, R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK,
S_030CCC_TOKEN_MASK(0xbfff) | S_030CCC_REG_MASK(0xff) | S_030CCC_REG_DROP_ON_STALL(0));
radeon_emit(cs, S_030CCC_TOKEN_MASK(0xbfff) | S_030CCC_REG_MASK(0xff) | S_030CCC_REG_DROP_ON_STALL(0));
/* Enable SQTT perf counters for all CUs. */
radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
S_030CD0_SH0_MASK(0xffff) | S_030CD0_SH1_MASK(0xffff));
radeon_emit(cs, S_030CD0_SH0_MASK(0xffff) | S_030CD0_SH1_MASK(0xffff));
radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);