gen7/pipeline: Re-arrange stencil parameters to match gen8
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+10
-11
@@ -227,27 +227,26 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
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bool has_stencil = false; /* enable if subpass has stencil? */
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struct GEN7_DEPTH_STENCIL_STATE state = {
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.DepthTestEnable = info->depthTestEnable,
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.DepthBufferWriteEnable = info->depthWriteEnable,
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.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
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.DoubleSidedStencilEnable = true,
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/* Is this what we need to do? */
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.StencilBufferWriteEnable = has_stencil,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
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.StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
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.StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
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.DoubleSidedStencilEnable = true,
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.BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
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.BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
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.BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
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.BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
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.DepthTestEnable = info->depthTestEnable,
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.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
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.DepthBufferWriteEnable = info->depthWriteEnable,
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.BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
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.BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
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};
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GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
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}
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