intel/compiler: Discount NOPs from instruction counts
Scheduler changes can cause changes in the number of instructions due to this workaround, so just don't include NOPs in the instruction counts to prevent shader-db noise. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
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@@ -1714,7 +1714,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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* effect is already counted in spill/fill counts.
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*/
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int spill_count = 0, fill_count = 0;
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int loop_count = 0, send_count = 0;
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int loop_count = 0, send_count = 0, nop_count = 0;
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bool is_accum_used = false;
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struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
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@@ -1744,6 +1744,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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inst->dst.component_size(inst->exec_size) > REG_SIZE) {
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brw_NOP(p);
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last_insn_offset = p->next_insn_offset;
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/* In order to avoid spurious instruction count differences when the
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* instruction schedule changes, keep track of the number of inserted
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* NOPs.
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*/
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nop_count++;
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}
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/* GEN:BUG:14010017096:
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@@ -2459,7 +2465,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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"Promoted %u constants, "
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"compacted %d to %d bytes.",
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_mesa_shader_stage_to_abbrev(stage),
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dispatch_width, before_size / 16,
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dispatch_width, before_size / 16 - nop_count,
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loop_count, cfg->cycle_count,
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spill_count, fill_count, send_count,
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shader_stats.scheduler_mode,
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@@ -2467,7 +2473,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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before_size, after_size);
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if (stats) {
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stats->dispatch_width = dispatch_width;
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stats->instructions = before_size / 16;
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stats->instructions = before_size / 16 - nop_count;
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stats->loops = loop_count;
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stats->cycles = cfg->cycle_count;
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stats->spills = spill_count;
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