ir3: Add cat7 sleep instruction

Has short and long variants, long seem to be ~20 times longer.
The exact difference between it and a bunch of nops is unknown.

The emission of this instruction were not observed in the wild.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14419>

src/freedreno/ir3/instr-a3xx.h

@@ -361,6 +361,7 @@ typedef enum {
    /* category 7: */
    OPC_BAR             = _OPC(7, 0),
    OPC_FENCE           = _OPC(7, 1),
+   OPC_SLEEP           = _OPC(7, 2),
    OPC_ICINV           = _OPC(7, 3),
    OPC_DCCLN           = _OPC(7, 4),
    OPC_DCINV           = _OPC(7, 5),

src/freedreno/ir3/ir3_lexer.l

@@ -382,6 +382,7 @@ static int parse_reg(const char *str)
                                   /* category 7: */
 "bar"                             return TOKEN(T_OP_BAR);
 "fence"                           return TOKEN(T_OP_FENCE);
+"sleep.l"                         return TOKEN(T_OP_SLEEP);
 "icinv"                           return TOKEN(T_OP_ICINV);
 "dccln.all"                       return TOKEN(T_OP_DCCLN);
 "dcinv.all"                       return TOKEN(T_OP_DCINV);

src/freedreno/ir3/ir3_parser.y

@@ -621,6 +621,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
 /* category 7: */
 %token <tok> T_OP_BAR
 %token <tok> T_OP_FENCE
+%token <tok> T_OP_SLEEP
 %token <tok> T_OP_ICINV
 %token <tok> T_OP_DCCLN
 %token <tok> T_OP_DCINV
@@ -1295,6 +1296,7 @@ cat7_data_cache:   T_OP_DCCLN              { new_instr(OPC_DCCLN); }
 
 cat7_instr:        cat7_barrier
 |                  cat7_data_cache
+|                  T_OP_SLEEP              { new_instr(OPC_SLEEP); }
 |                  T_OP_ICINV              { new_instr(OPC_ICINV); }
 
 raw_instr: T_RAW   {new_instr(OPC_META_RAW)->raw.value = $1;}

src/freedreno/ir3/tests/disasm.c

@@ -418,6 +418,7 @@ static const struct test {
    INSTR_6XX(e0fa0000_00000000, "fence.g.l.r.w"),
    INSTR_6XX(e09a0000_00000000, "fence.r.w"),
    INSTR_6XX(f0420000_00000000, "(sy)bar.g"),
+   INSTR_6XX(e1080000_00000000, "sleep.l"),
    INSTR_6XX(e2080000_00000000, "dccln.all"),
 
    INSTR_6XX(ffffffff_ffffffff, "raw 0xFFFFFFFFFFFFFFFF"),

src/freedreno/isa/ir3-cat7.xml

@@ -80,6 +80,37 @@ SOFTWARE.
 	</encode>
 </bitset>
 
+<enum name="#sleep-duration">
+	<value val="0" display=".s">
+		<doc>
+			Short sleep
+		</doc>
+	</value>
+	<value val="1" display=".l">
+		<doc>
+			Long sleep, around 20x longer than short
+		</doc>
+	</value>
+</enum>
+
+<bitset name="sleep" extends="#instruction-cat7">
+	<doc>
+		Short/Long Sleep
+		TODO: how is it different from a bunch of nops?
+	</doc>
+	<display>
+		{SY}{JP}{NAME}{DURATION}
+	</display>
+	<pattern low="45" high="50">xxxxxx</pattern>
+	<field   pos="51"          name="DURATION" type="#sleep-duration"/>
+	<pattern low="52" high="54">xxx</pattern>
+	<pattern low="55" high="58">0010</pattern>
+	<encode>
+		<!-- TODO: read duration -->
+		<map name="DURATION">1</map>
+	</encode>
+</bitset>
+
 <bitset name="icinv" extends="#instruction-cat7">
 	<doc>
 		Seem to be Instruction Cache Invalidate, supported by the fact