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radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven only

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-11-07 16:12:56 +01:00
parent 24e9004708
commit e616743dab
1 changed files with 4 additions and 4 deletions
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src/gallium/drivers/radeonsi/si_state_draw.c
+4 -4
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@@ -1405,11 +1405,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
/* GFX9 scissor bug workaround. This must be done before VPORT scissor
* registers are changed. There is also a more efficient but more
* involved alternative workaround.
/* Vega10/Raven scissor bug workaround. This must be done before VPORT
* scissor registers are changed. There is also a more efficient but
* more involved alternative workaround.
*/
if (sctx->b.chip_class == GFX9 &&
if ((sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN) &&
si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(sctx);