i965: Use 64-bit writes for occlusion queries.
The hardware seems to use the length of the PIPE_CONTROL command to indicate whether the write is 64-bits or 32-bits. Which makes sense for immediate writes. Daniel discovered this by writing a pattern into the query object bo and noticing that the high 32-bits were left intact, even on those pipe control writes that seemingly worked. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Eric Anholt <eric@anholt.net>
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@@ -91,7 +91,7 @@ static void
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write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
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{
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if (intel->gen >= 6) {
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BEGIN_BATCH(8);
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BEGIN_BATCH(9);
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/* workaround: CS stall required before depth stall. */
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OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
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@@ -99,7 +99,7 @@ write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
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OUT_BATCH(0); /* write address */
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OUT_BATCH(0); /* write data */
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OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
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OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
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OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
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PIPE_CONTROL_WRITE_DEPTH_COUNT);
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OUT_RELOC(query_bo,
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@@ -107,6 +107,7 @@ write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
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PIPE_CONTROL_GLOBAL_GTT_WRITE |
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(idx * sizeof(uint64_t)));
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OUT_BATCH(0);
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OUT_BATCH(0);
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ADVANCE_BATCH();
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} else {
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BEGIN_BATCH(4);
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