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r300: move depth output rewrite out of NQSSADCE

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This commit is contained in:
Maciej Cencora
2009-07-04 16:50:25 +02:00
parent f79ef95df4
commit e43cc28c1b
3 changed files with 46 additions and 49 deletions
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src/mesa/drivers/dri/r300/r300_fragprog_common.c
+44 -4
View File
@@ -239,6 +239,46 @@ static void build_state(
}
}
static void rewrite_depth_out(struct gl_program *prog)
{
struct prog_instruction *inst;
for (inst = prog->Instructions; inst->Opcode != OPCODE_END; ++inst) {
if (inst->DstReg.File != PROGRAM_OUTPUT || inst->DstReg.Index != FRAG_RESULT_DEPTH)
continue;
if (inst->DstReg.WriteMask & WRITEMASK_Z) {
inst->DstReg.WriteMask = WRITEMASK_W;
} else {
inst->DstReg.WriteMask = 0;
continue;
}
switch (inst->Opcode) {
case OPCODE_FRC:
case OPCODE_MOV:
inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
break;
case OPCODE_ADD:
case OPCODE_MAX:
case OPCODE_MIN:
case OPCODE_MUL:
inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
break;
case OPCODE_CMP:
case OPCODE_MAD:
inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
inst->SrcReg[2] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[2]);
break;
default:
// Scalar instructions needn't be reswizzled
break;
}
}
}
void r300TranslateFragmentShader(GLcontext *ctx, struct r300_fragment_program *fp)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
@@ -260,6 +300,8 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct r300_fragment_program *f
rewriteFog(&compiler);
rewrite_depth_out(compiler.program);
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
struct radeon_program_transformation transformations[] = {
{ &r500_transform_TEX, &compiler },
@@ -287,16 +329,14 @@ void r300TranslateFragmentShader(GLcontext *ctx, struct r300_fragment_program *f
struct radeon_nqssadce_descr nqssadce = {
.Init = &nqssadce_init,
.IsNativeSwizzle = &r500FPIsNativeSwizzle,
.BuildSwizzle = &r500FPBuildSwizzle,
.RewriteDepthOut = GL_TRUE
.BuildSwizzle = &r500FPBuildSwizzle
};
radeonNqssaDce(ctx, compiler.program, &nqssadce);
} else {
struct radeon_nqssadce_descr nqssadce = {
.Init = &nqssadce_init,
.IsNativeSwizzle = &r300FPIsNativeSwizzle,
.BuildSwizzle = &r300FPBuildSwizzle,
.RewriteDepthOut = GL_TRUE
.BuildSwizzle = &r300FPBuildSwizzle
};
radeonNqssaDce(ctx, compiler.program, &nqssadce);
}
src/mesa/drivers/dri/r300/radeon_nqssadce.c
+1 -40
View File
@@ -56,7 +56,7 @@ static struct register_state *get_reg_state(struct nqssadce_state* s, GLuint fil
*
* @note Works correctly only for X, Y, Z, W swizzles, not for constant swizzles.
*/
static struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg)
struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg)
{
struct prog_src_register tmp = srcreg;
int i;
@@ -121,40 +121,6 @@ static struct prog_instruction* track_used_srcreg(struct nqssadce_state* s,
return inst;
}
static void rewrite_depth_out(struct prog_instruction *inst)
{
if (inst->DstReg.WriteMask & WRITEMASK_Z) {
inst->DstReg.WriteMask = WRITEMASK_W;
} else {
inst->DstReg.WriteMask = 0;
return;
}
switch (inst->Opcode) {
case OPCODE_FRC:
case OPCODE_MOV:
inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
break;
case OPCODE_ADD:
case OPCODE_MAX:
case OPCODE_MIN:
case OPCODE_MUL:
inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
break;
case OPCODE_CMP:
case OPCODE_MAD:
inst->SrcReg[0] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[0]);
inst->SrcReg[1] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[1]);
inst->SrcReg[2] = lmul_swizzle(SWIZZLE_ZZZZ, inst->SrcReg[2]);
break;
default:
// Scalar instructions needn't be reswizzled
break;
}
}
static void unalias_srcregs(struct prog_instruction *inst, GLuint oldindex, GLuint newindex)
{
int nsrc = _mesa_num_inst_src_regs(inst->Opcode);
@@ -189,11 +155,6 @@ static void process_instruction(struct nqssadce_state* s)
return;
if (inst->Opcode != OPCODE_KIL) {
if (s->Descr->RewriteDepthOut) {
if (inst->DstReg.File == PROGRAM_OUTPUT && inst->DstReg.Index == FRAG_RESULT_DEPTH)
rewrite_depth_out(inst);
}
struct register_state *regstate = get_reg_state(s, inst->DstReg.File, inst->DstReg.Index);
if (!regstate) {
_mesa_problem(s->Ctx, "NqssaDce: bad destination register (%i[%i])\n",
src/mesa/drivers/dri/r300/radeon_nqssadce.h
+1 -5
View File
@@ -83,14 +83,10 @@ struct radeon_nqssadce_descr {
*/
void (*BuildSwizzle)(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
/**
* Rewrite instructions that write to DEPR.z to write to DEPR.w
* instead (rewriting is done *before* the WriteMask test).
*/
GLboolean RewriteDepthOut;
void *Data;
};
void radeonNqssaDce(GLcontext *ctx, struct gl_program *p, struct radeon_nqssadce_descr* descr);
struct prog_src_register lmul_swizzle(GLuint swizzle, struct prog_src_register srcreg);
#endif /* __RADEON_PROGRAM_NQSSADCE_H_ */