ac/surface: enable DCC computation for MSAA

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-11-23 22:29:26 +01:00
parent 6863651bbd
commit e3c0a5b6e8
3 changed files with 6 additions and 6 deletions
+2 -4
View File
@@ -586,7 +586,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
info->chip_class >= VI &&
!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
!compressed && AddrDccIn.numSamples <= 1 &&
!compressed &&
((config->info.array_size == 1 && config->info.depth == 1) ||
config->info.levels == 1);
@@ -927,9 +927,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
if (!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!compressed &&
in->swizzleMode != ADDR_SW_LINEAR &&
/* TODO: We could support DCC with MSAA. */
in->numSamples == 1) {
in->swizzleMode != ADDR_SW_LINEAR) {
ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
+2 -1
View File
@@ -155,7 +155,8 @@ radv_init_surface(struct radv_device *device,
(pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
device->physical_device->rad_info.chip_class < VI ||
create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC))
create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC) ||
pCreateInfo->samples >= 2)
surface->flags |= RADEON_SURF_DISABLE_DCC;
if (create_info->scanout)
surface->flags |= RADEON_SURF_SCANOUT;
+2 -1
View File
@@ -266,7 +266,8 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
if (rscreen->chip_class >= VI &&
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
ptex->nr_samples >= 2))
flags |= RADEON_SURF_DISABLE_DCC;
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {