radeonsi: don't disable L2 caching for staging textures

Uncached access can be slow if the box is not aligned nicely.
Also, caching in L2 might enable bigger PCIe bursts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>

src/gallium/drivers/radeonsi/si_texture.c

@@ -1798,19 +1798,6 @@ static void *si_texture_transfer_map(struct pipe_context *ctx, struct pipe_resou
       unsigned bo_usage = usage & PIPE_MAP_READ ? PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
       unsigned bo_flags = SI_RESOURCE_FLAG_FORCE_LINEAR | SI_RESOURCE_FLAG_DRIVER_INTERNAL;
 
-      /* The pixel shader has a bad access pattern for linear textures.
-       * If a pixel shader is used to blit to/from staging, don't disable caches.
-       *
-       * MSAA, depth/stencil textures, and compressed textures use the pixel shader
-       * to blit.
-       */
-      if (texture->nr_samples <= 1 &&
-          !tex->is_depth &&
-          !util_format_is_compressed(texture->format) &&
-          /* Texture uploads with DCC use the pixel shader to blit */
-          (!(usage & PIPE_MAP_WRITE) || !vi_dcc_enabled(tex, level)))
-         bo_flags |= SI_RESOURCE_FLAG_UNCACHED;
-
       si_init_temp_resource_from_box(&resource, texture, box, level, bo_usage,
                                      bo_flags);