nak: use standard methods and macros to improve readability
v2: Leave `Op::is_branch()` and `Op::no_scoreboard()` matches alone v3: Revert additional changes with unclear readability Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34372>
This commit is contained in:
@@ -563,7 +563,7 @@ impl<'a> VecRegAllocator<'a> {
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fn move_ssa_to_reg(&mut self, ssa: SSAValue, new_reg: u32) {
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if let Some(old_reg) = self.ra.try_get_reg(ssa) {
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assert!(self.evicted.get(&ssa).is_none());
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assert!(!self.evicted.contains_key(&ssa));
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assert!(!self.reg_is_pinned(old_reg));
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if new_reg == old_reg {
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@@ -209,12 +209,7 @@ impl BarAlloc {
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}
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pub fn try_find_free_bar(&self) -> Option<u8> {
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for bar in 0..self.num_bars {
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if self.bar_is_free(bar) {
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return Some(bar);
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}
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}
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None
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(0..self.num_bars).find(|&bar| self.bar_is_free(bar))
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}
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pub fn free_some_bar(&mut self) -> u8 {
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@@ -230,12 +225,7 @@ impl BarAlloc {
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}
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pub fn get_bar_for_dep(&self, dep: usize) -> Option<u8> {
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for bar in 0..self.num_bars {
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if self.bar_dep[usize::from(bar)] == dep {
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return Some(bar);
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}
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}
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None
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(0..self.num_bars).find(|&bar| self.bar_dep[usize::from(bar)] == dep)
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}
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}
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@@ -347,8 +337,7 @@ fn calc_delays(f: &mut Function, sm: &dyn ShaderModel) -> u32 {
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let mut cycle = 0_u32;
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// Vector mapping IP to start cycle
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let mut instr_cycle = Vec::new();
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instr_cycle.resize(b.instrs.len(), 0_u32);
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let mut instr_cycle = vec![0; b.instrs.len()];
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// Maps registers to RegUse<ip, src_dst_idx>. Predicates are
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// represented by src_idx = usize::MAX.
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@@ -502,9 +502,7 @@ impl<'a> ShaderFromNir<'a> {
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}
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fn alu_src_is_saturated(&self, src: &nir_alu_src) -> bool {
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self.saturated
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.get(&(src.src.as_def() as *const _))
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.is_some()
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self.saturated.contains(&(src.src.as_def() as *const _))
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}
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fn parse_alu(&mut self, b: &mut impl SSABuilder, alu: &nir_alu_instr) {
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@@ -3783,7 +3781,7 @@ impl<'a> ShaderFromNir<'a> {
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/* Next block in the NIR CF list */
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let next_block = nb.cf_node.next().unwrap().as_block().unwrap();
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if else_target as *const _ == next_block as *const _ {
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if std::ptr::eq(else_target, next_block) {
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self.emit_pred_jump(
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&mut b,
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nb,
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@@ -3792,7 +3790,7 @@ impl<'a> ShaderFromNir<'a> {
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target,
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else_target,
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);
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} else if target as *const _ == next_block as *const _ {
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} else if std::ptr::eq(target, next_block) {
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self.emit_pred_jump(
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&mut b,
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nb,
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@@ -583,10 +583,9 @@ impl SrcRef {
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pub fn is_bindless_cbuf(&self) -> bool {
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match self {
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SrcRef::CBuf(cbuf) => match cbuf.buf {
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CBuf::BindlessSSA(_) | CBuf::BindlessUGPR(_) => true,
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_ => false,
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},
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SrcRef::CBuf(cbuf) => {
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matches!(cbuf.buf, CBuf::BindlessSSA(_) | CBuf::BindlessUGPR(_))
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}
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_ => false,
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}
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}
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@@ -1264,7 +1263,7 @@ fn all_dsts_uniform(dsts: &[Dst]) -> bool {
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Dst::Reg(r) => r.is_uniform(),
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Dst::SSA(r) => r.file().unwrap().is_uniform(),
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};
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assert!(uniform == None || uniform == Some(dst_uniform));
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assert!(uniform.is_none() || uniform == Some(dst_uniform));
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uniform = Some(dst_uniform);
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}
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uniform == Some(true)
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@@ -3303,7 +3302,7 @@ pub struct OpIAbs {
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impl Foldable for OpIAbs {
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fn fold(&self, _sm: &dyn ShaderModel, f: &mut OpFoldData<'_>) {
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let src = f.get_u32_src(self, &self.src);
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let dst = (src as i32).abs() as u32;
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let dst = (src as i32).unsigned_abs();
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f.set_u32_dst(self, &self.dst, dst);
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}
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}
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@@ -4609,12 +4608,10 @@ impl OpPrmt {
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return None;
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}
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if let Some(sel) = self.sel.as_u32(SrcType::ALU) {
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self.sel.as_u32(SrcType::ALU).map(|sel| {
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// The top 16 bits are ignored
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Some(PrmtSel(sel as u16))
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} else {
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None
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}
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PrmtSel(sel as u16)
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})
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}
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/// Reduces the sel immediate, if any.
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@@ -462,7 +462,7 @@ fn legalize_instr(
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// vector sources or as multiple components in the same
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// source, we need to make a copy so it can get assigned to
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// multiple different registers.
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if vec_comps.get(&ssa).is_some() {
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if vec_comps.contains(&ssa) {
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let copy = b.alloc_ssa(ssa.file());
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b.copy_to(copy.into(), ssa.into());
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new_vec[usize::from(c)] = copy;
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@@ -98,7 +98,7 @@ fn lower_par_copy(pc: OpParCopy, sm: &dyn ShaderModel) -> MappedInstrs {
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for (i, (dst, _)) in pc.dsts_srcs.iter().enumerate() {
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// Destinations must be pairwise unique
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let reg = dst.as_reg().unwrap();
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assert!(reg_to_idx.get(reg).is_none());
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assert!(!reg_to_idx.contains_key(reg));
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// Everything must be scalar
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assert!(reg.comps() == 1);
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@@ -43,7 +43,7 @@ impl DeadCodePass {
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match dst {
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Dst::SSA(ssa) => {
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for val in ssa.iter() {
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if self.live_ssa.get(val).is_some() {
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if self.live_ssa.contains(val) {
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return true;
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}
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}
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@@ -55,7 +55,7 @@ impl DeadCodePass {
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}
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fn is_phi_live(&self, id: u32) -> bool {
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self.live_phi.get(&id).is_some()
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self.live_phi.contains(&id)
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}
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fn is_instr_live(&self, instr: &Instr) -> bool {
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@@ -517,7 +517,7 @@ pub fn encode_header(
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}
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let uses_underestimate =
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fs_key.map_or(false, |key| key.uses_underestimate);
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fs_key.is_some_and(|key| key.uses_underestimate);
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// This isn't so much a "Do we write multiple render targets?" bit
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// as a "Should color0 be broadcast to all render targets?" bit. In
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@@ -541,7 +541,7 @@ pub fn encode_header(
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match &shader_info.stage {
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ShaderStageInfo::Fragment(stage) => {
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let zs_self_dep = fs_key.map_or(false, |key| key.zs_self_dep);
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let zs_self_dep = fs_key.is_some_and(|key| key.zs_self_dep);
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sph.set_kills_pixels(stage.uses_kill || zs_self_dep);
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sph.set_does_interlock(stage.does_interlock);
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}
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@@ -1034,7 +1034,7 @@ fn spill_values<S: Spill>(
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let ip = pb
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.phi_srcs_ip()
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.or_else(|| pb.branch_ip())
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.unwrap_or_else(|| pb.instrs.len());
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.unwrap_or(pb.instrs.len());
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pb.instrs.splice(ip..ip, instrs.into_iter());
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}
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}
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@@ -79,9 +79,9 @@ impl<const SIZE: usize> SSAValueArray<SIZE> {
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packed: NonZeroU32::MAX,
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}; SIZE],
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};
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for i in 0..comps.len() {
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r.v[i] = comps[i];
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}
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r.v[..comps.len()].copy_from_slice(comps);
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if comps.len() < SIZE {
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r.v[SIZE - 1].packed =
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(comps.len() as u32).wrapping_neg().try_into().unwrap();
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@@ -238,9 +238,8 @@ impl<'a> CoalesceGraph<'a> {
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let nodes = MergedIter::new(a_nodes.into_iter(), b_nodes.into_iter());
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self.sets[a].nodes = nodes
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.map(|n| {
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.inspect(|&n| {
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self.nodes[n].set = a;
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n
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})
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.collect();
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