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radeonsi: remove RADEON_FLAG_READ_ONLY

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It's not used much and it doubles the number of heaps.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29510>
This commit is contained in:
Marek Olšák
2024-05-31 17:49:50 -04:00
committed by Marge Bot
parent 21d6d44e96
commit e303aae145
10 changed files with 8 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/r600/compute_memory_pool.c
+1 -2
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@@ -415,8 +415,7 @@ void compute_memory_demote_item(struct compute_memory_pool *pool,
* temporary buffer. Download is skipped for items:
* - Not mapped for reading or writing (PIPE_MAP_DISCARD_RANGE).
* - Not writable by the device. */
if ((item->status & (ITEM_MAPPED_FOR_READING|ITEM_MAPPED_FOR_WRITING)) &&
!(r600_resource(dst)->flags & RADEON_FLAG_READ_ONLY)) {
if ((item->status & (ITEM_MAPPED_FOR_READING|ITEM_MAPPED_FOR_WRITING))) {
u_box_1d(item->start_in_dw * 4, item->size_in_dw * 4, &box);
src/gallium/drivers/r600/r600_buffer_common.c
+1 -2
View File
@@ -615,8 +615,7 @@ r600_buffer_from_user_memory(struct pipe_screen *screen,
util_range_add(&rbuffer->b.b, &rbuffer->b.valid_buffer_range, 0, templ->width0);
/* Convert a user pointer to a buffer. */
rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0,
templ->usage == PIPE_USAGE_IMMUTABLE? RADEON_FLAG_READ_ONLY : 0);
rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0, 0);
if (!rbuffer->buf) {
FREE(rbuffer);
return NULL;
src/gallium/drivers/radeonsi/si_buffer.c
-3
View File
@@ -103,9 +103,6 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
if (sscreen->debug_flags & DBG(NO_WC))
res->flags &= ~RADEON_FLAG_GTT_WC;
if (res->b.b.flags & SI_RESOURCE_FLAG_READ_ONLY)
res->flags |= RADEON_FLAG_READ_ONLY;
if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
res->flags |= RADEON_FLAG_32BIT;
src/gallium/drivers/radeonsi/si_pipe.h
+1 -2
View File
@@ -104,10 +104,9 @@ struct ac_llvm_compiler;
#define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define SI_RESOURCE_FLAG_DISCARDABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) /* Discard instead of evict. */
#define SI_RESOURCE_FLAG_DRIVER_INTERNAL (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
#define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
#define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
#define SI_RESOURCE_AUX_PLANE (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
enum si_has_gs {
GS_OFF,
src/gallium/drivers/radeonsi/si_shader.c
-1
View File
@@ -922,7 +922,6 @@ static void *pre_upload_binary(struct si_screen *sscreen, struct si_shader *shad
shader->bo = si_aligned_buffer_create(
&sscreen->b,
SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT |
(dma_upload || sscreen->info.cpdma_prefetch_writes_memory ? 0 : SI_RESOURCE_FLAG_READ_ONLY) |
(dma_upload ? PIPE_RESOURCE_FLAG_UNMAPPABLE : 0),
PIPE_USAGE_IMMUTABLE, align(aligned_size, SI_CPDMA_ALIGNMENT), 256);
if (!shader->bo)
src/gallium/drivers/radeonsi/si_state_draw.cpp
-1
View File
@@ -344,7 +344,6 @@ static bool si_update_shaders(struct si_context *sctx)
*/
struct si_resource *bo = si_aligned_buffer_create(
&sctx->screen->b,
(sctx->screen->info.cpdma_prefetch_writes_memory ? 0 : SI_RESOURCE_FLAG_READ_ONLY) |
SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_IMMUTABLE, align(total_size, SI_CPDMA_ALIGNMENT), 256);
src/gallium/include/winsys/radeon_winsys.h
-8
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@@ -54,7 +54,6 @@ enum radeon_bo_flag
RADEON_FLAG_NO_SUBALLOC = (1 << 2),
RADEON_FLAG_SPARSE = (1 << 3),
RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
RADEON_FLAG_READ_ONLY = (1 << 5),
RADEON_FLAG_32BIT = (1 << 6),
RADEON_FLAG_ENCRYPTED = (1 << 7),
RADEON_FLAG_GL2_BYPASS = (1 << 8), /* only gfx9 and newer */
@@ -78,8 +77,6 @@ si_res_print_flags(enum radeon_bo_flag flags) {
fprintf(stderr, "SPARSE ");
if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING)
fprintf(stderr, "NO_INTERPROCESS_SHARING ");
if (flags & RADEON_FLAG_READ_ONLY)
fprintf(stderr, "READ_ONLY ");
if (flags & RADEON_FLAG_32BIT)
fprintf(stderr, "32BIT ");
if (flags & RADEON_FLAG_ENCRYPTED)
@@ -813,7 +810,6 @@ radeon_bo_drop_reference(struct radeon_winsys *rws, struct pb_buffer_lean *dst)
* the allocation cache (pb_cache).
*/
#define RADEON_HEAP_BIT_VRAM (1 << 0) /* if false, it's GTT */
#define RADEON_HEAP_BIT_READ_ONLY (1 << 1) /* both VRAM and GTT */
#define RADEON_HEAP_BIT_32BIT (1 << 2) /* both VRAM and GTT */
#define RADEON_HEAP_BIT_ENCRYPTED (1 << 3) /* both VRAM and GTT */
@@ -841,8 +837,6 @@ static inline unsigned radeon_flags_from_heap(int heap)
unsigned flags = RADEON_FLAG_NO_INTERPROCESS_SHARING;
if (heap & RADEON_HEAP_BIT_READ_ONLY)
flags |= RADEON_FLAG_READ_ONLY;
if (heap & RADEON_HEAP_BIT_32BIT)
flags |= RADEON_FLAG_32BIT;
if (heap & RADEON_HEAP_BIT_ENCRYPTED)
@@ -918,8 +912,6 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain, enum radeo
int heap = 0;
if (flags & RADEON_FLAG_READ_ONLY)
heap |= RADEON_HEAP_BIT_READ_ONLY;
if (flags & RADEON_FLAG_32BIT)
heap |= RADEON_HEAP_BIT_32BIT;
if (flags & RADEON_FLAG_ENCRYPTED)
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+1 -3
View File
@@ -581,11 +581,9 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
goto error_va_alloc;
unsigned vm_flags = AMDGPU_VM_PAGE_READABLE |
AMDGPU_VM_PAGE_WRITEABLE |
AMDGPU_VM_PAGE_EXECUTABLE;
if (!(flags & RADEON_FLAG_READ_ONLY))
vm_flags |= AMDGPU_VM_PAGE_WRITEABLE;
if (flags & RADEON_FLAG_GL2_BYPASS)
vm_flags |= AMDGPU_VM_MTYPE_UC;
src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp
+1 -2
View File
@@ -987,8 +987,7 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
RADEON_DOMAIN_VRAM,
(radeon_bo_flag)
(RADEON_FLAG_NO_INTERPROCESS_SHARING |
RADEON_FLAG_GTT_WC |
RADEON_FLAG_READ_ONLY));
RADEON_FLAG_GTT_WC));
if (!preamble_bo)
return false;
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+3 -8
View File
@@ -1086,14 +1086,9 @@ static struct pb_buffer_lean *radeon_winsys_bo_from_ptr(struct radeon_winsys *rw
memset(&args, 0, sizeof(args));
args.addr = (uintptr_t)pointer;
args.size = align(size, ws->info.gart_page_size);
if (flags & RADEON_FLAG_READ_ONLY)
args.flags = RADEON_GEM_USERPTR_READONLY |
RADEON_GEM_USERPTR_VALIDATE;
else
args.flags = RADEON_GEM_USERPTR_ANONONLY |
RADEON_GEM_USERPTR_REGISTER |
RADEON_GEM_USERPTR_VALIDATE;
args.flags = RADEON_GEM_USERPTR_ANONONLY |
RADEON_GEM_USERPTR_REGISTER |
RADEON_GEM_USERPTR_VALIDATE;
if (drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
&args, sizeof(args))) {