mesa,gallium: remove pipe_shader_type_from_mesa
It's not needed as we unify pipe_shader_type and mesa_shader_stage. Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
This commit is contained in:
@@ -3296,7 +3296,7 @@ ntt_should_vectorize_io(unsigned align, unsigned bit_size,
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static nir_variable_mode
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ntt_no_indirects_mask(nir_shader *s, struct pipe_screen *screen)
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{
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unsigned pipe_stage = pipe_shader_type_from_mesa(s->info.stage);
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unsigned pipe_stage = s->info.stage;
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unsigned indirect_mask = 0;
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if (!(s->options->support_indirect_inputs & BITFIELD_BIT(pipe_stage))) {
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@@ -3319,7 +3319,7 @@ ntt_optimize_nir(struct nir_shader *s, struct pipe_screen *screen,
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const struct nir_to_tgsi_options *options)
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{
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bool progress;
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unsigned pipe_stage = pipe_shader_type_from_mesa(s->info.stage);
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unsigned pipe_stage = s->info.stage;
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unsigned control_flow_depth =
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screen->shader_caps[pipe_stage].max_control_flow_depth;
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do {
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@@ -3683,7 +3683,7 @@ ntt_fix_nir_options(struct pipe_screen *screen, struct nir_shader *s,
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{
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const struct nir_shader_compiler_options *options = s->options;
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bool lower_fsqrt =
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!screen->shader_caps[pipe_shader_type_from_mesa(s->info.stage)].tgsi_sqrt_supported;
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!screen->shader_caps[s->info.stage].tgsi_sqrt_supported;
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bool force_indirect_unrolling_sampler =
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screen->caps.glsl_feature_level < 400;
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@@ -3888,7 +3888,7 @@ const void *nir_to_tgsi_options(struct nir_shader *s,
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struct ntt_compile *c;
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const void *tgsi_tokens;
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nir_variable_mode no_indirects_mask = ntt_no_indirects_mask(s, screen);
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bool native_integers = screen->shader_caps[pipe_shader_type_from_mesa(s->info.stage)].integers;
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bool native_integers = screen->shader_caps[s->info.stage].integers;
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const struct nir_shader_compiler_options *original_options = s->options;
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ntt_fix_nir_options(screen, s, options);
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@@ -3970,7 +3970,7 @@ const void *nir_to_tgsi_options(struct nir_shader *s,
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NIR_PASS(_, s, nir_opt_combine_barriers, NULL, NULL);
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if (screen->shader_caps[pipe_shader_type_from_mesa(s->info.stage)].integers) {
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if (screen->shader_caps[s->info.stage].integers) {
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NIR_PASS(_, s, nir_lower_bool_to_int32);
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} else {
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NIR_PASS(_, s, nir_lower_int_to_float);
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@@ -4014,7 +4014,7 @@ const void *nir_to_tgsi_options(struct nir_shader *s,
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c->s = s;
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c->native_integers = native_integers;
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c->ureg = ureg_create(pipe_shader_type_from_mesa(s->info.stage));
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c->ureg = ureg_create(s->info.stage);
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ureg_setup_shader_info(c->ureg, &s->info);
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if (s->info.use_legacy_math_rules && screen->caps.legacy_math_rules)
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ureg_property(c->ureg, TGSI_PROPERTY_LEGACY_MATH_RULES, 1);
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@@ -253,11 +253,10 @@ void nir_tgsi_scan_shader(const struct nir_shader *nir,
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{
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unsigned i;
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info->processor = pipe_shader_type_from_mesa(nir->info.stage);
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info->processor = nir->info.stage;
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info->num_instructions = 1;
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info->properties[TGSI_PROPERTY_NEXT_SHADER] =
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pipe_shader_type_from_mesa(nir->info.next_stage);
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info->properties[TGSI_PROPERTY_NEXT_SHADER] = nir->info.next_stage;
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if (nir->info.stage == MESA_SHADER_VERTEX) {
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info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
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@@ -58,18 +58,6 @@ tgsi_get_sysval_semantic(unsigned sysval);
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enum tgsi_interpolate_mode
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tgsi_get_interp_mode(enum glsl_interp_mode mode, bool color);
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static inline mesa_shader_stage
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pipe_shader_type_from_mesa(mesa_shader_stage stage)
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{
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STATIC_ASSERT((mesa_shader_stage) MESA_SHADER_VERTEX == MESA_SHADER_VERTEX);
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STATIC_ASSERT((mesa_shader_stage) MESA_SHADER_FRAGMENT == MESA_SHADER_FRAGMENT);
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STATIC_ASSERT((mesa_shader_stage) MESA_SHADER_TESS_CTRL == MESA_SHADER_TESS_CTRL);
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STATIC_ASSERT((mesa_shader_stage) MESA_SHADER_TESS_EVAL == MESA_SHADER_TESS_EVAL);
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STATIC_ASSERT((mesa_shader_stage) MESA_SHADER_GEOMETRY == MESA_SHADER_GEOMETRY);
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STATIC_ASSERT((mesa_shader_stage) MESA_SHADER_COMPUTE == MESA_SHADER_COMPUTE);
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return (mesa_shader_stage)stage;
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}
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static inline mesa_shader_stage
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tgsi_processor_to_shader_stage(unsigned processor)
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{
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@@ -2410,7 +2410,7 @@ ureg_setup_shader_info(struct ureg_program *ureg,
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switch (info->stage) {
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case MESA_SHADER_VERTEX:
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ureg_setup_clipdist_info(ureg, info);
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ureg_set_next_shader_processor(ureg, pipe_shader_type_from_mesa(info->next_stage));
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ureg_set_next_shader_processor(ureg, info->next_stage);
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break;
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case MESA_SHADER_TESS_CTRL:
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ureg_setup_tess_ctrl_shader(ureg, info);
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@@ -2418,7 +2418,7 @@ ureg_setup_shader_info(struct ureg_program *ureg,
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case MESA_SHADER_TESS_EVAL:
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ureg_setup_tess_eval_shader(ureg, info);
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ureg_setup_clipdist_info(ureg, info);
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ureg_set_next_shader_processor(ureg, pipe_shader_type_from_mesa(info->next_stage));
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ureg_set_next_shader_processor(ureg, info->next_stage);
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break;
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case MESA_SHADER_GEOMETRY:
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ureg_setup_geometry_shader(ureg, info);
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@@ -91,7 +91,7 @@ util_live_shader_cache_get(struct pipe_context *ctx,
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nir_serialize(&blob, state->ir.nir, true);
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ir_binary = blob.data;
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ir_size = blob.size;
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stage = pipe_shader_type_from_mesa(state->ir.nir->info.stage);
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stage = state->ir.nir->info.stage;
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} else {
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assert(0);
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return NULL;
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@@ -1860,7 +1860,7 @@ agx_shader_initialize(struct agx_device *dev, struct agx_uncompiled_shader *so,
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NIR_PASS(_, nir, agx_nir_lower_sample_intrinsics, true);
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}
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so->type = pipe_shader_type_from_mesa(nir->info.stage);
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so->type = nir->info.stage;
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if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
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nir->info.stage = MESA_SHADER_VERTEX;
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@@ -1808,7 +1808,7 @@ ntr_should_vectorize_io(unsigned align, unsigned bit_size, unsigned num_componen
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static nir_variable_mode
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ntr_no_indirects_mask(nir_shader *s, struct pipe_screen *screen)
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{
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unsigned pipe_stage = pipe_shader_type_from_mesa(s->info.stage);
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unsigned pipe_stage = s->info.stage;
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unsigned indirect_mask = nir_var_shader_in | nir_var_shader_out;
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if (!screen->shader_caps[pipe_stage].indirect_temp_addr) {
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@@ -2116,7 +2116,7 @@ nir_to_rc(struct nir_shader *s, struct pipe_screen *screen,
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}
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c->s = s;
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c->ureg = ureg_create(pipe_shader_type_from_mesa(s->info.stage));
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c->ureg = ureg_create(s->info.stage);
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ureg_setup_shader_info(c->ureg, &s->info);
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if (s->info.use_legacy_math_rules && screen->caps.legacy_math_rules)
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ureg_property(c->ureg, TGSI_PROPERTY_LEGACY_MATH_RULES, 1);
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@@ -147,7 +147,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
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int processor = sel->ir_type == PIPE_SHADER_IR_TGSI ?
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tgsi_get_processor_type(sel->tokens):
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pipe_shader_type_from_mesa(sel->nir->info.stage);
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sel->nir->info.stage;
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bool dump = r600_can_dump_shader(&rctx->screen->b, processor);
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@@ -743,10 +743,8 @@ get_shader_program_completion_status(struct gl_context *ctx,
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if (linked->Program->variants)
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sh = linked->Program->variants->driver_shader;
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unsigned type = pipe_shader_type_from_mesa(i);
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if (sh &&
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!screen->is_parallel_shader_compilation_finished(screen, sh, type))
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!screen->is_parallel_shader_compilation_finished(screen, sh, i))
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return false;
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}
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return true;
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@@ -69,7 +69,6 @@ st_bind_atomics(struct st_context *st, struct gl_program *prog,
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mesa_shader_stage stage)
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{
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unsigned i;
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mesa_shader_stage shader_type = pipe_shader_type_from_mesa(stage);
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if (!prog || !st->pipe->set_shader_buffers || st->has_hw_atomics)
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return;
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@@ -87,11 +86,11 @@ st_bind_atomics(struct st_context *st, struct gl_program *prog,
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st_binding_to_sb(&st->ctx->AtomicBufferBindings[atomic->Binding], &sb,
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st->ctx->Const.ShaderStorageBufferOffsetAlignment);
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st->pipe->set_shader_buffers(st->pipe, shader_type,
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st->pipe->set_shader_buffers(st->pipe, stage,
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buffer_base + atomic->Binding, 1, &sb, 0x1);
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used_bindings = MAX2(atomic->Binding + 1, used_bindings);
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}
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st->last_used_atomic_bindings[shader_type] = used_bindings;
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st->last_used_atomic_bindings[stage] = used_bindings;
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}
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void
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@@ -69,23 +69,22 @@ st_unbind_unused_cb0(struct st_context *st, mesa_shader_stage shader_type)
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void
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st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_stage stage)
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{
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mesa_shader_stage shader_type = pipe_shader_type_from_mesa(stage);
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if (!prog) {
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st_unbind_unused_cb0(st, shader_type);
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st_unbind_unused_cb0(st, stage);
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return;
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}
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struct gl_program_parameter_list *params = prog->Parameters;
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assert(shader_type == MESA_SHADER_VERTEX ||
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shader_type == MESA_SHADER_FRAGMENT ||
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shader_type == MESA_SHADER_GEOMETRY ||
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shader_type == MESA_SHADER_TESS_CTRL ||
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shader_type == MESA_SHADER_TESS_EVAL ||
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shader_type == MESA_SHADER_COMPUTE);
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assert(stage == MESA_SHADER_VERTEX ||
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stage == MESA_SHADER_FRAGMENT ||
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stage == MESA_SHADER_GEOMETRY ||
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stage == MESA_SHADER_TESS_CTRL ||
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stage == MESA_SHADER_TESS_EVAL ||
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stage == MESA_SHADER_COMPUTE);
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/* update the ATI constants before rendering */
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if (shader_type == MESA_SHADER_FRAGMENT && prog->ati_fs) {
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if (stage == MESA_SHADER_FRAGMENT && prog->ati_fs) {
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struct ati_fragment_shader *ati_fs = prog->ati_fs;
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unsigned c;
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@@ -144,7 +143,7 @@ st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_
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_mesa_upload_state_parameters(st->ctx, params, ptr);
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u_upload_unmap(pipe->const_uploader);
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pipe->set_constant_buffer(pipe, shader_type, 0, true, &cb);
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pipe->set_constant_buffer(pipe, stage, 0, true, &cb);
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/* Set inlinable constants. This is more involved because state
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* parameters are uploaded directly above instead of being loaded
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@@ -168,7 +167,7 @@ st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_
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values[i] = constbuf[prog->info.inlinable_uniform_dw_offsets[i]].u;
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}
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pipe->set_inlinable_constants(pipe, shader_type,
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pipe->set_inlinable_constants(pipe, stage,
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prog->info.num_inlinable_uniforms,
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values);
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}
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@@ -183,7 +182,7 @@ st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_
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if (params->StateFlags)
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_mesa_load_state_parameters(st->ctx, params);
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pipe->set_constant_buffer(pipe, shader_type, 0, false, &cb);
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pipe->set_constant_buffer(pipe, stage, 0, false, &cb);
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/* Set inlinable constants. */
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unsigned num_inlinable_uniforms = prog->info.num_inlinable_uniforms;
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@@ -194,15 +193,15 @@ st_upload_constants(struct st_context *st, struct gl_program *prog, mesa_shader_
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for (unsigned i = 0; i < num_inlinable_uniforms; i++)
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values[i] = constbuf[prog->info.inlinable_uniform_dw_offsets[i]].u;
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pipe->set_inlinable_constants(pipe, shader_type,
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pipe->set_inlinable_constants(pipe, stage,
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prog->info.num_inlinable_uniforms,
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values);
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}
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}
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st->state.constbuf0_enabled_shader_mask |= 1 << shader_type;
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st->state.constbuf0_enabled_shader_mask |= 1 << stage;
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} else {
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st_unbind_unused_cb0(st, shader_type);
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st_unbind_unused_cb0(st, stage);
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}
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}
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@@ -599,7 +599,7 @@ st_link_glsl_to_nir(struct gl_context *ctx,
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if (shader) {
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struct gl_program *p = shader->Program;
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if (p && p->variants) {
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mesa_shader_stage type = pipe_shader_type_from_mesa(shader->Stage);
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mesa_shader_stage type = shader->Stage;
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driver_handles[type] = p->variants->driver_shader;
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}
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}
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@@ -581,7 +581,7 @@ void
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st_make_bound_samplers_resident(struct st_context *st,
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struct gl_program *prog)
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{
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mesa_shader_stage shader = pipe_shader_type_from_mesa(prog->info.stage);
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mesa_shader_stage shader = prog->info.stage;
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struct st_bound_handles *bound_handles = &st->bound_texture_handles[shader];
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struct pipe_context *pipe = st->pipe;
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GLuint64 handle;
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@@ -628,7 +628,7 @@ void
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st_make_bound_images_resident(struct st_context *st,
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struct gl_program *prog)
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{
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mesa_shader_stage shader = pipe_shader_type_from_mesa(prog->info.stage);
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mesa_shader_stage shader = prog->info.stage;
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struct st_bound_handles *bound_handles = &st->bound_image_handles[shader];
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struct pipe_context *pipe = st->pipe;
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GLuint64 handle;
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