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R6xx/R7xx: r300 -> r600 symbols

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This commit is contained in:
Alex Deucher
2009-04-09 10:55:41 -04:00
parent 4138bdb3b1
commit e24e4ae2e8
28 changed files with 3595 additions and 3595 deletions
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src/mesa/drivers/dri/r600/r600_cmdbuf.c
+247 -247
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@@ -55,7 +55,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r600_state.h"
#include "radeon_reg.h"
#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
#define R600_VAP_PVS_UPLOAD_ADDRESS 0x2200
# define RADEON_ONE_REG_WR (1 << 15)
/** # of dwords reserved for additional instructions that may need to be written
@@ -63,9 +63,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define SPACE_FOR_FLUSHING 4
static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
static unsigned packet0_count(r600ContextPtr r600, uint32_t *pkt)
{
if (r300->radeon.radeonScreen->kernel_mm) {
if (r600->radeon.radeonScreen->kernel_mm) {
return ((((*pkt) >> 16) & 0x3FFF) + 1);
} else {
drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
@@ -79,12 +79,12 @@ static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i;
if (!r300->radeon.radeonScreen->kernel_mm) {
if (!r600->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
@@ -98,38 +98,38 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
ndw = cmd.vpu.count * 4;
if (ndw) {
if (r300->vap_flush_needed) {
if (r600->vap_flush_needed) {
BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
/* flush processing vertices */
OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0);
OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
r300->vap_flush_needed = GL_FALSE;
OUT_BATCH_REGVAL(R600_SC_SCREENDOOR, 0xffffff);
OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
r600->vap_flush_needed = GL_FALSE;
} else {
BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
}
OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
OUT_BATCH_REGVAL(R600_VAP_PVS_UPLOAD_ADDRESS, addr);
OUT_BATCH(CP_PACKET0(R600_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
for (i = 0; i < ndw; i++) {
OUT_BATCH(atom->cmd[i+1]);
}
OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
END_BATCH();
}
}
void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i, sz;
int type, clamp, stride;
if (!r300->radeon.radeonScreen->kernel_mm) {
if (!r600->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
BEGIN_BATCH_NO_AUTOSTATE(dwords);
@@ -165,42 +165,42 @@ void emit_r500fp(GLcontext *ctx, struct radeon_state_atom * atom)
static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
int numtmus = packet0_count(r600, r600->hw.tex.offset.cmd);
int notexture = 0;
if (numtmus) {
int i;
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
radeonTexObj *t = r600->hw.textures[i];
if (!t)
notexture = 1;
}
if (r300->radeon.radeonScreen->kernel_mm && notexture) {
if (r600->radeon.radeonScreen->kernel_mm && notexture) {
return;
}
BEGIN_BATCH_NO_AUTOSTATE(4 * numtmus);
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
radeonTexObj *t = r600->hw.textures[i];
OUT_BATCH_REGSEQ(R600_TX_OFFSET_0 + (i * 4), 1);
if (t && !t->image_override) {
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!t) {
OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]);
} else { /* override cases */
if (t->bo) {
OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!r300->radeon.radeonScreen->kernel_mm) {
} else if (!r600->radeon.radeonScreen->kernel_mm) {
OUT_BATCH(t->override_offset);
}
else
OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
OUT_BATCH(r600->radeon.radeonScreen->texOffset[0]);
}
}
END_BATCH();
@@ -209,13 +209,13 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
struct radeon_renderbuffer *rrb;
uint32_t cbpitch;
uint32_t offset = r300->radeon.state.color.draw_offset;
uint32_t offset = r600->radeon.state.color.draw_offset;
rrb = radeon_get_colorbuffer(&r300->radeon);
rrb = radeon_get_colorbuffer(&r600->radeon);
if (!rrb || !rrb->bo) {
fprintf(stderr, "no rrb\n");
return;
@@ -223,34 +223,34 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->cpp == 4)
cbpitch |= R300_COLOR_FORMAT_ARGB8888;
cbpitch |= R600_COLOR_FORMAT_ARGB8888;
else
cbpitch |= R300_COLOR_FORMAT_RGB565;
cbpitch |= R600_COLOR_FORMAT_RGB565;
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
cbpitch |= R300_COLOR_TILE_ENABLE;
cbpitch |= R600_COLOR_TILE_ENABLE;
BEGIN_BATCH_NO_AUTOSTATE(8);
OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1);
OUT_BATCH_RELOC(offset, rrb->bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
OUT_BATCH_REGSEQ(R600_RB3D_COLORPITCH0, 1);
OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (r600->radeon.radeonScreen->driScreen->dri2.enabled) {
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
BEGIN_BATCH_NO_AUTOSTATE(3);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2);
OUT_BATCH(0);
OUT_BATCH((rrb->width << R300_SCISSORS_X_SHIFT) |
(rrb->height << R300_SCISSORS_Y_SHIFT));
OUT_BATCH((rrb->width << R600_SCISSORS_X_SHIFT) |
(rrb->height << R600_SCISSORS_Y_SHIFT));
END_BATCH();
} else {
BEGIN_BATCH_NO_AUTOSTATE(3);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
(R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
OUT_BATCH(((rrb->width + R300_SCISSORS_OFFSET) << R300_SCISSORS_X_SHIFT) |
((rrb->height + R300_SCISSORS_OFFSET) << R300_SCISSORS_Y_SHIFT));
OUT_BATCH_REGSEQ(R600_SC_SCISSORS_TL, 2);
OUT_BATCH((R600_SCISSORS_OFFSET << R600_SCISSORS_X_SHIFT) |
(R600_SCISSORS_OFFSET << R600_SCISSORS_Y_SHIFT));
OUT_BATCH(((rrb->width + R600_SCISSORS_OFFSET) << R600_SCISSORS_X_SHIFT) |
((rrb->height + R600_SCISSORS_OFFSET) << R600_SCISSORS_Y_SHIFT));
END_BATCH();
}
}
@@ -258,45 +258,45 @@ static void emit_cb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
struct radeon_renderbuffer *rrb;
uint32_t zbpitch;
rrb = radeon_get_depthbuffer(&r300->radeon);
rrb = radeon_get_depthbuffer(&r600->radeon);
if (!rrb)
return;
zbpitch = (rrb->pitch / rrb->cpp);
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
zbpitch |= R300_DEPTHMACROTILE_ENABLE;
zbpitch |= R600_DEPTHMACROTILE_ENABLE;
}
if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
zbpitch |= R300_DEPTHMICROTILE_TILED;
zbpitch |= R600_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(6);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, zbpitch);
OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, zbpitch);
END_BATCH();
}
static void emit_zstencil_format(GLcontext *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
struct radeon_renderbuffer *rrb;
uint32_t format = 0;
rrb = radeon_get_depthbuffer(&r300->radeon);
rrb = radeon_get_depthbuffer(&r600->radeon);
if (!rrb)
format = 0;
else {
if (rrb->cpp == 2)
format = R300_DEPTHFORMAT_16BIT_INT_Z;
format = R600_DEPTHFORMAT_16BIT_INT_Z;
else if (rrb->cpp == 4)
format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
format = R600_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
}
OUT_BATCH(atom->cmd[0]);
@@ -315,12 +315,12 @@ static int check_always(GLcontext *ctx, struct radeon_state_atom *atom)
static int check_variable(GLcontext *ctx, struct radeon_state_atom *atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
r600ContextPtr r600 = R600_CONTEXT(ctx);
int cnt;
if (atom->cmd[0] == CP_PACKET2) {
return 0;
}
cnt = packet0_count(r300, atom->cmd);
cnt = packet0_count(r600, atom->cmd);
return cnt ? cnt + 1 : 0;
}
@@ -350,320 +350,320 @@ int check_r500fp_const(GLcontext *ctx, struct radeon_state_atom *atom)
#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
do { \
r300->hw.ATOM.cmd_size = (SZ); \
r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
r300->hw.ATOM.name = #ATOM; \
r300->hw.ATOM.idx = (IDX); \
r300->hw.ATOM.check = check_##CHK; \
r300->hw.ATOM.dirty = GL_FALSE; \
r300->radeon.hw.max_state_size += (SZ); \
insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
r600->hw.ATOM.cmd_size = (SZ); \
r600->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
r600->hw.ATOM.name = #ATOM; \
r600->hw.ATOM.idx = (IDX); \
r600->hw.ATOM.check = check_##CHK; \
r600->hw.ATOM.dirty = GL_FALSE; \
r600->radeon.hw.max_state_size += (SZ); \
insert_at_tail(&r600->radeon.hw.atomlist, &r600->hw.ATOM); \
} while (0)
/**
* Allocate memory for the command buffer and initialize the state atom
* list. Note that the initial hardware state is set by r300InitState().
* list. Note that the initial hardware state is set by r600InitState().
*/
void r300InitCmdBuf(r300ContextPtr r300)
void r600InitCmdBuf(r600ContextPtr r600)
{
int mtu;
int has_tcl = 1;
int is_r500 = 0;
int i;
if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
r600->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
mtu = r600->radeon.glCtx->Const.MaxTextureUnits;
if (RADEON_DEBUG & DEBUG_TEXTURE) {
fprintf(stderr, "Using %d maximum texture units..\n", mtu);
}
/* Setup the atom linked list */
make_empty_list(&r300->radeon.hw.atomlist);
r300->radeon.hw.atomlist.name = "atom-list";
make_empty_list(&r600->radeon.hw.atomlist);
r600->radeon.hw.atomlist.name = "atom-list";
/* Initialize state atoms */
ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
ALLOC_STATE(vpt, always, R600_VPT_CMDSIZE, 0);
r600->hw.vpt.cmd[R600_VPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VPORT_XSCALE, 6);
ALLOC_STATE(vap_cntl, always, R600_VAP_CNTL_SIZE, 0);
r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_STATE_FLUSH_REG, 1);
r600->hw.vap_cntl.cmd[R600_VAP_CNTL_FLUSH_1] = 0;
r600->hw.vap_cntl.cmd[R600_VAP_CNTL_CMD] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL, 1);
if (is_r500) {
ALLOC_STATE(vap_index_offset, always, 2, 0);
r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
r300->hw.vap_index_offset.cmd[1] = 0;
r600->hw.vap_index_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
r600->hw.vap_index_offset.cmd[1] = 0;
}
ALLOC_STATE(vte, always, 3, 0);
r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
r600->hw.vte.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SE_VTE_CNTL, 2);
ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
r600->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VF_MAX_VTX_INDX, 2);
ALLOC_STATE(vap_cntl_status, always, 2, 0);
r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
r600->hw.vap_cntl_status.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CNTL_STATUS, 1);
ALLOC_STATE(vir[0], variable, R600_VIR_CMDSIZE, 0);
r600->hw.vir[0].cmd[R600_VIR_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_0, 1);
ALLOC_STATE(vir[1], variable, R600_VIR_CMDSIZE, 1);
r600->hw.vir[1].cmd[R600_VIR_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PROG_STREAM_CNTL_EXT_0, 1);
ALLOC_STATE(vic, always, R600_VIC_CMDSIZE, 0);
r600->hw.vic.cmd[R600_VIC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_VTX_STATE_CNTL, 2);
ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
r600->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
if (has_tcl) {
ALLOC_STATE(vap_clip_cntl, always, 2, 0);
r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
r600->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_CLIP_CNTL, 1);
ALLOC_STATE(vap_clip, always, 5, 0);
r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
r600->hw.vap_clip.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_VAP_GB_VERT_CLIP_ADJ, 4);
ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
r600->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
}
ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
r300->hw.vof.cmd[R300_VOF_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
ALLOC_STATE(vof, always, R600_VOF_CMDSIZE, 0);
r600->hw.vof.cmd[R600_VOF_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_OUTPUT_VTX_FMT_0, 2);
if (has_tcl) {
ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
r300->hw.pvs.cmd[R300_PVS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
ALLOC_STATE(pvs, always, R600_PVS_CMDSIZE, 0);
r600->hw.pvs.cmd[R600_PVS_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_VAP_PVS_CODE_CNTL_0, 3);
}
ALLOC_STATE(gb_enable, always, 2, 0);
r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
r600->hw.gb_enable.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_ENABLE, 1);
ALLOC_STATE(gb_misc, always, R600_GB_MISC_CMDSIZE, 0);
r600->hw.gb_misc.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GB_MSPOS0, 5);
ALLOC_STATE(txe, always, R600_TXE_CMDSIZE, 0);
r600->hw.txe.cmd[R600_TXE_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_ENABLE, 1);
ALLOC_STATE(ga_point_s0, always, 5, 0);
r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
r600->hw.ga_point_s0.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_S0, 4);
ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
r600->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_TRIANGLE_STIPPLE, 1);
ALLOC_STATE(ps, always, R600_PS_CMDSIZE, 0);
r600->hw.ps.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_SIZE, 1);
ALLOC_STATE(ga_point_minmax, always, 4, 0);
r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
r600->hw.ga_point_minmax.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POINT_MINMAX, 3);
ALLOC_STATE(lcntl, always, 2, 0);
r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
r600->hw.lcntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_CNTL, 1);
ALLOC_STATE(ga_line_stipple, always, 4, 0);
r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
r600->hw.ga_line_stipple.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_LINE_STIPPLE_VALUE, 3);
ALLOC_STATE(shade, always, 5, 0);
r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
r600->hw.shade.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_ENHANCE, 4);
ALLOC_STATE(polygon_mode, always, 4, 0);
r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
r600->hw.polygon_mode.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_POLY_MODE, 3);
ALLOC_STATE(fogp, always, 3, 0);
r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
r600->hw.fogp.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_GA_FOG_SCALE, 2);
ALLOC_STATE(zbias_cntl, always, 2, 0);
r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
r600->hw.zbias_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_TEX_WRAP, 1);
ALLOC_STATE(zbs, always, R600_ZBS_CMDSIZE, 0);
r600->hw.zbs.cmd[R600_ZBS_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_FRONT_SCALE, 4);
ALLOC_STATE(occlusion_cntl, always, 2, 0);
r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
r600->hw.occlusion_cntl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_POLY_OFFSET_ENABLE, 1);
ALLOC_STATE(cul, always, R600_CUL_CMDSIZE, 0);
r600->hw.cul.cmd[R600_CUL_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_CULL_MODE, 1);
ALLOC_STATE(su_depth_scale, always, 3, 0);
r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
r600->hw.su_depth_scale.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SU_DEPTH_SCALE, 2);
ALLOC_STATE(rc, always, R600_RC_CMDSIZE, 0);
r600->hw.rc.cmd[R600_RC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_COUNT, 2);
if (is_r500) {
ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_IP_0, 16);
for (i = 0; i < 8; i++) {
r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
r600->hw.ri.cmd[R600_RI_CMD_0 + i +1] =
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
}
ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_RS_INST_0, 1);
} else {
ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
ALLOC_STATE(ri, always, R600_RI_CMDSIZE, 0);
r600->hw.ri.cmd[R600_RI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_IP_0, 8);
ALLOC_STATE(rr, variable, R600_RR_CMDSIZE, 0);
r600->hw.rr.cmd[R600_RR_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RS_INST_0, 1);
}
ALLOC_STATE(sc_hyperz, always, 3, 0);
r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
r600->hw.sc_hyperz.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_HYPERZ, 2);
ALLOC_STATE(sc_screendoor, always, 2, 0);
r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
r600->hw.sc_screendoor.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_SC_SCREENDOOR, 1);
ALLOC_STATE(us_out_fmt, always, 6, 0);
r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
r600->hw.us_out_fmt.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_OUT_FMT, 5);
if (is_r500) {
ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
r600->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CONFIG, 2);
r600->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
r600->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
r600->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r600->radeon.radeonScreen, R500_US_FC_CTRL, 1);
r600->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
r300->hw.r500fp.emit = emit_r500fp;
r600->hw.r500fp.cmd[R600_FPI_CMD_0] =
cmdr500fp(r600->radeon.radeonScreen, 0, 0, 0, 0);
r600->hw.r500fp.emit = emit_r500fp;
ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
r300->hw.r500fp_const.emit = emit_r500fp;
r600->hw.r500fp_const.cmd[R600_FPI_CMD_0] =
cmdr500fp(r600->radeon.radeonScreen, 0, 0, 1, 0);
r600->hw.r500fp_const.emit = emit_r500fp;
} else {
ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
ALLOC_STATE(fp, always, R600_FP_CMDSIZE, 0);
r600->hw.fp.cmd[R600_FP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CONFIG, 3);
r600->hw.fp.cmd[R600_FP_CMD_1] = cmdpacket0(r600->radeon.radeonScreen, R600_US_CODE_ADDR_0, 4);
ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
ALLOC_STATE(fpt, variable, R600_FPT_CMDSIZE, 0);
r600->hw.fpt.cmd[R600_FPT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_TEX_INST_0, 0);
ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
ALLOC_STATE(fpi[0], variable, R600_FPI_CMDSIZE, 0);
r600->hw.fpi[0].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_INST_0, 1);
ALLOC_STATE(fpi[1], variable, R600_FPI_CMDSIZE, 1);
r600->hw.fpi[1].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_RGB_ADDR_0, 1);
ALLOC_STATE(fpi[2], variable, R600_FPI_CMDSIZE, 2);
r600->hw.fpi[2].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_INST_0, 1);
ALLOC_STATE(fpi[3], variable, R600_FPI_CMDSIZE, 3);
r600->hw.fpi[3].cmd[R600_FPI_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_US_ALU_ALPHA_ADDR_0, 1);
ALLOC_STATE(fpp, variable, R600_FPP_CMDSIZE, 0);
r600->hw.fpp.cmd[R600_FPP_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_PFS_PARAM_0_X, 0);
}
ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
ALLOC_STATE(fogs, always, R600_FOGS_CMDSIZE, 0);
r600->hw.fogs.cmd[R600_FOGS_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_BLEND, 1);
ALLOC_STATE(fogc, always, R600_FOGC_CMDSIZE, 0);
r600->hw.fogc.cmd[R600_FOGC_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_FOG_COLOR_R, 3);
ALLOC_STATE(at, always, R600_AT_CMDSIZE, 0);
r600->hw.at.cmd[R600_AT_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_ALPHA_FUNC, 2);
ALLOC_STATE(fg_depth_src, always, 2, 0);
r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
r600->hw.fg_depth_src.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_FG_DEPTH_SRC, 1);
ALLOC_STATE(rb3d_cctl, always, 2, 0);
r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
r600->hw.rb3d_cctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CCTL, 1);
ALLOC_STATE(bld, always, R600_BLD_CMDSIZE, 0);
r600->hw.bld.cmd[R600_BLD_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_CBLEND, 2);
ALLOC_STATE(cmk, always, R600_CMK_CMDSIZE, 0);
r600->hw.cmk.cmd[R600_CMK_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
if (is_r500) {
ALLOC_STATE(blend_color, always, 3, 0);
r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
} else {
ALLOC_STATE(blend_color, always, 2, 0);
r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
r600->hw.blend_color.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_BLEND_COLOR, 1);
}
ALLOC_STATE(rop, always, 2, 0);
r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
r300->hw.cb.emit = &emit_cb_offset;
r600->hw.rop.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, always, R600_CB_CMDSIZE, 0);
r600->hw.cb.emit = &emit_cb_offset;
ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
r600->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_DITHER_CTL, 9);
ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
r600->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_RB3D_AARESOLVE_CTL, 1);
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
r300->hw.zs.cmd[R300_ZS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
r600->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
ALLOC_STATE(zs, always, R600_ZS_CMDSIZE, 0);
r600->hw.zs.cmd[R600_ZS_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_ZB_CNTL, 3);
ALLOC_STATE(zstencil_format, always, 5, 0);
r300->hw.zstencil_format.cmd[0] =
cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
r300->hw.zstencil_format.emit = emit_zstencil_format;
r600->hw.zstencil_format.cmd[0] =
cmdpacket0(r600->radeon.radeonScreen, R600_ZB_FORMAT, 4);
r600->hw.zstencil_format.emit = emit_zstencil_format;
ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
r300->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb, always, R600_ZB_CMDSIZE, 0);
r600->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
r600->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_DEPTHCLEARVALUE, 1);
ALLOC_STATE(unk4F30, always, 3, 0);
r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
r600->hw.unk4F30.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, 0x4F30, 2);
ALLOC_STATE(zb_hiz_offset, always, 2, 0);
r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
r600->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_OFFSET, 1);
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
r600->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r600->radeon.radeonScreen, R600_ZB_HIZ_PITCH, 1);
/* VPU only on TCL */
if (has_tcl) {
int i;
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
r300->hw.vpi.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
r300->hw.vpi.emit = emit_vpu;
ALLOC_STATE(vpi, vpu, R600_VPI_CMDSIZE, 0);
r600->hw.vpi.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_PVS_CODE_START, 0);
r600->hw.vpi.emit = emit_vpu;
if (is_r500) {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
r600->hw.vpp.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R500_PVS_CONST_START, 0);
r600->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
r300->hw.vps.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
r600->hw.vps.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
r600->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
r600->hw.vpucp[i].cmd[0] =
cmdvpu(r600->radeon.radeonScreen,
R500_PVS_UCP_START + i, 1);
r300->hw.vpucp[i].emit = emit_vpu;
r600->hw.vpucp[i].emit = emit_vpu;
}
} else {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vpp, vpu, R600_VPP_CMDSIZE, 0);
r600->hw.vpp.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_PVS_CONST_START, 0);
r600->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
r300->hw.vps.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R600_VPS_CMDSIZE, 0);
r600->hw.vps.cmd[0] =
cmdvpu(r600->radeon.radeonScreen, R600_POINT_VPORT_SCALE_OFFSET, 1);
r600->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
R300_PVS_UCP_START + i, 1);
r300->hw.vpucp[i].emit = emit_vpu;
ALLOC_STATE(vpucp[i], vpu, R600_VPUCP_CMDSIZE, 0);
r600->hw.vpucp[i].cmd[0] =
cmdvpu(r600->radeon.radeonScreen,
R600_PVS_UCP_START + i, 1);
r600->hw.vpucp[i].emit = emit_vpu;
}
}
}
/* Textures */
ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
r600->hw.tex.filter.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER0_0, 0);
ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
r600->hw.tex.filter_1.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_FILTER1_0, 0);
ALLOC_STATE(tex.size, variable, mtu + 1, 0);
r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
r600->hw.tex.size.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_SIZE_0, 0);
ALLOC_STATE(tex.format, variable, mtu + 1, 0);
r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
r600->hw.tex.format.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT_0, 0);
ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
r600->hw.tex.pitch.cmd[R600_TEX_CMD_0] = cmdpacket0(r600->radeon.radeonScreen, R600_TX_FORMAT2_0, 0);
ALLOC_STATE(tex.offset, variable, 1, 0);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
r300->hw.tex.offset.emit = &emit_tex_offsets;
r600->hw.tex.offset.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_OFFSET_0, 0);
r600->hw.tex.offset.emit = &emit_tex_offsets;
ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
r600->hw.tex.chroma_key.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_CHROMA_KEY_0, 0);
ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
r600->hw.tex.border_color.cmd[R600_TEX_CMD_0] =
cmdpacket0(r600->radeon.radeonScreen, R600_TX_BORDER_COLOR_0, 0);
r300->radeon.hw.is_dirty = GL_TRUE;
r300->radeon.hw.all_dirty = GL_TRUE;
r600->radeon.hw.is_dirty = GL_TRUE;
r600->radeon.hw.all_dirty = GL_TRUE;
rcommonInitCmdBuf(&r300->radeon);
rcommonInitCmdBuf(&r600->radeon);
}
src/mesa/drivers/dri/r600/r600_cmdbuf.h
+1 -1
View File
@@ -38,7 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r600_context.h"
extern void r300InitCmdBuf(r300ContextPtr r300);
extern void r600InitCmdBuf(r600ContextPtr r600);
void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom);
int check_vpu(GLcontext *ctx, struct radeon_state_atom *atom);
src/mesa/drivers/dri/r600/r600_context.c
+76 -76
View File
@@ -155,14 +155,14 @@ const struct dri_extension gl_20_extension[] = {
};
extern struct tnl_pipeline_stage _r300_render_stage;
extern const struct tnl_pipeline_stage _r300_tcl_stage;
extern struct tnl_pipeline_stage _r600_render_stage;
extern const struct tnl_pipeline_stage _r600_tcl_stage;
static const struct tnl_pipeline_stage *r300_pipeline[] = {
static const struct tnl_pipeline_stage *r600_pipeline[] = {
/* Try and go straight to t&l
*/
&_r300_tcl_stage,
&_r600_tcl_stage,
/* Catch any t&l fallbacks
*/
@@ -186,12 +186,12 @@ static const struct tnl_pipeline_stage *r300_pipeline[] = {
/* Else do them here.
*/
&_r300_render_stage,
&_r600_render_stage,
&_tnl_render_stage, /* FALLBACK */
0,
};
static void r300RunPipeline(GLcontext * ctx)
static void r600RunPipeline(GLcontext * ctx)
{
_mesa_lock_context_textures(ctx);
@@ -202,7 +202,7 @@ static void r300RunPipeline(GLcontext * ctx)
_mesa_unlock_context_textures(ctx);
}
static void r300_get_lock(radeonContextPtr rmesa)
static void r600_get_lock(radeonContextPtr rmesa)
{
drm_radeon_sarea_t *sarea = rmesa->sarea;
@@ -213,79 +213,79 @@ static void r300_get_lock(radeonContextPtr rmesa)
}
}
static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
static void r600_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
/* please flush pipe do all pending work */
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_SC_SCREENDOOR, 1));
R600_SC_SCREENDOOR, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_SC_SCREENDOOR, 1));
R600_SC_SCREENDOOR, 1));
radeon_cs_write_dword(cs, 0x00FFFFFF);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_SC_HYPERZ, 1));
R600_SC_HYPERZ, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_US_CONFIG, 1));
R600_US_CONFIG, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_ZB_CNTL, 1));
R600_ZB_CNTL, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_RB3D_DSTCACHE_CTLSTAT, 1));
radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
R600_RB3D_DSTCACHE_CTLSTAT, 1));
radeon_cs_write_dword(cs, R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_ZB_ZCACHE_CTLSTAT, 1));
radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
R600_ZB_ZCACHE_CTLSTAT, 1));
radeon_cs_write_dword(cs, R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
R300_WAIT_3D | R300_WAIT_3D_CLEAN));
}
static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
static void r600_vtbl_pre_emit_atoms(radeonContextPtr radeon)
{
r300ContextPtr r300 = (r300ContextPtr)radeon;
r600ContextPtr r600 = (r600ContextPtr)radeon;
BATCH_LOCALS(radeon);
r300->vap_flush_needed = GL_TRUE;
r600->vap_flush_needed = GL_TRUE;
cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
OUT_BATCH_REGVAL(R600_TX_INVALTAGS, R600_TX_FLUSH);
END_BATCH();
end_3d(radeon);
}
static void r300_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
static void r600_fallback(GLcontext *ctx, GLuint bit, GLboolean mode)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
r600ContextPtr r600 = R600_CONTEXT(ctx);
if (mode)
r300->radeon.Fallback |= bit;
r600->radeon.Fallback |= bit;
else
r300->radeon.Fallback &= ~bit;
r600->radeon.Fallback &= ~bit;
}
static void r300_init_vtbl(radeonContextPtr radeon)
static void r600_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r300_get_lock;
radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
radeon->vtbl.swtcl_flush = r300_swtcl_flush;
radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
radeon->vtbl.fallback = r300_fallback;
radeon->vtbl.get_lock = r600_get_lock;
radeon->vtbl.update_viewport_offset = r600UpdateViewportOffset;
radeon->vtbl.emit_cs_header = r600_vtbl_emit_cs_header;
radeon->vtbl.swtcl_flush = r600_swtcl_flush;
radeon->vtbl.pre_emit_atoms = r600_vtbl_pre_emit_atoms;
radeon->vtbl.fallback = r600_fallback;
}
/* Create the device specific rendering context.
*/
GLboolean r300CreateContext(const __GLcontextModes * glVisual,
GLboolean r600CreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate)
{
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
struct dd_function_table functions;
r300ContextPtr r300;
r600ContextPtr r600;
GLcontext *ctx;
int tcl_mode;
@@ -293,52 +293,52 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
assert(driContextPriv);
assert(screen);
/* Allocate the R300 context */
r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
if (!r300)
/* Allocate the R600 context */
r600 = (r600ContextPtr) CALLOC(sizeof(*r600));
if (!r600)
return GL_FALSE;
if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
hw_tcl_on = future_hw_tcl_on = 0;
r300_init_vtbl(&r300->radeon);
r600_init_vtbl(&r600->radeon);
/* Parse configuration files.
* Do this here so that initialMaxAnisotropy is set before we create
* the default textures.
*/
driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "r300");
r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache,
driParseConfigFiles(&r600->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "r600");
r600->radeon.initialMaxAnisotropy = driQueryOptionf(&r600->radeon.optionCache,
"def_max_anisotropy");
/* Init default driver functions then plug in our R300-specific functions
/* Init default driver functions then plug in our R600-specific functions
* (the texture functions are especially important)
*/
_mesa_init_driver_functions(&functions);
r300InitIoctlFuncs(&functions);
r300InitStateFuncs(&functions);
r300InitTextureFuncs(&functions);
r300InitShaderFuncs(&functions);
r600InitIoctlFuncs(&functions);
r600InitStateFuncs(&functions);
r600InitTextureFuncs(&functions);
r600InitShaderFuncs(&functions);
if (!radeonInitContext(&r300->radeon, &functions,
if (!radeonInitContext(&r600->radeon, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
FREE(r300);
FREE(r600);
return GL_FALSE;
}
/* Init r300 context data */
/* Init r600 context data */
/* Set the maximum texture size small enough that we can guarentee that
* all texture units can bind a maximal texture and have them both in
* texturable memory at once.
*/
ctx = r300->radeon.glCtx;
ctx = r600->radeon.glCtx;
ctx->Const.MaxTextureImageUnits =
driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
driQueryOptioni(&r600->radeon.optionCache, "texture_image_units");
ctx->Const.MaxTextureCoordUnits =
driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
driQueryOptioni(&r600->radeon.optionCache, "texture_coord_units");
ctx->Const.MaxTextureUnits =
MIN2(ctx->Const.MaxTextureImageUnits,
ctx->Const.MaxTextureCoordUnits);
@@ -352,13 +352,13 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
ctx->Const.MaxPointSize = R600_POINTSIZE_MAX;
ctx->Const.MaxPointSizeAA = R600_POINTSIZE_MAX;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
ctx->Const.MaxLineWidth = R600_LINESIZE_MAX;
ctx->Const.MaxLineWidthAA = R600_LINESIZE_MAX;
/* Needs further modifications */
#if 0
@@ -380,7 +380,7 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline(ctx);
_tnl_install_pipeline(ctx, r300_pipeline);
_tnl_install_pipeline(ctx, r600_pipeline);
/* Try and keep materials and vertices separate:
*/
@@ -420,50 +420,50 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
driInitExtensions(ctx, card_extensions, GL_TRUE);
if (r300->radeon.radeonScreen->kernel_mm)
if (r600->radeon.radeonScreen->kernel_mm)
driInitExtensions(ctx, mm_extensions, GL_FALSE);
if (driQueryOptionb
(&r300->radeon.optionCache, "disable_stencil_two_side"))
(&r600->radeon.optionCache, "disable_stencil_two_side"))
_mesa_disable_extension(ctx, "GL_EXT_stencil_two_side");
if (r300->radeon.glCtx->Mesa_DXTn
&& !driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc")) {
if (r600->radeon.glCtx->Mesa_DXTn
&& !driQueryOptionb(&r600->radeon.optionCache, "disable_s3tc")) {
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
_mesa_enable_extension(ctx, "GL_S3_s3tc");
} else
if (driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable"))
if (driQueryOptionb(&r600->radeon.optionCache, "force_s3tc_enable"))
{
_mesa_enable_extension(ctx, "GL_EXT_texture_compression_s3tc");
}
r300->disable_lowimpact_fallback =
driQueryOptionb(&r300->radeon.optionCache,
r600->disable_lowimpact_fallback =
driQueryOptionb(&r600->radeon.optionCache,
"disable_lowimpact_fallback");
radeon_fbo_init(&r300->radeon);
radeon_fbo_init(&r600->radeon);
radeonInitSpanFuncs( ctx );
r300InitCmdBuf(r300);
r300InitState(r300);
r600InitCmdBuf(r600);
r600InitState(r600);
if (!(screen->chip_flags & RADEON_CHIPSET_TCL))
r300InitSwtcl(ctx);
r600InitSwtcl(ctx);
TNL_CONTEXT(ctx)->Driver.RunPipeline = r300RunPipeline;
TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline;
tcl_mode = driQueryOptioni(&r300->radeon.optionCache, "tcl_mode");
if (driQueryOptionb(&r300->radeon.optionCache, "no_rast")) {
tcl_mode = driQueryOptioni(&r600->radeon.optionCache, "tcl_mode");
if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D acceleration\n");
#if R200_MERGED
FALLBACK(&r300->radeon, RADEON_FALLBACK_DISABLE, 1);
FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1);
#endif
}
if (tcl_mode == DRI_CONF_TCL_SW ||
!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
r300->radeon.radeonScreen->chip_flags &=
!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
r600->radeon.radeonScreen->chip_flags &=
~RADEON_CHIPSET_TCL;
fprintf(stderr, "Disabling HW TCL support\n");
}
TCL_FALLBACK(r300->radeon.glCtx,
TCL_FALLBACK(r600->radeon.glCtx,
RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
}
src/mesa/drivers/dri/r600/r600_context.h
+220 -220
View File
@@ -48,9 +48,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "main/mtypes.h"
#include "main/colormac.h"
struct r300_context;
typedef struct r300_context r300ContextRec;
typedef struct r300_context *r300ContextPtr;
struct r600_context;
typedef struct r600_context r600ContextRec;
typedef struct r600_context *r600ContextPtr;
#include "main/mm.h"
@@ -80,116 +80,116 @@ typedef struct r300_context *r300ContextPtr;
/* The blit width for texture uploads
*/
#define R300_BLIT_WIDTH_BYTES 1024
#define R300_MAX_TEXTURE_UNITS 8
#define R600_BLIT_WIDTH_BYTES 1024
#define R600_MAX_TEXTURE_UNITS 8
struct r300_texture_state {
struct r600_texture_state {
int tc_count; /* number of incoming texture coordinates from VAP */
};
#define R300_VPT_CMD_0 0
#define R300_VPT_XSCALE 1
#define R300_VPT_XOFFSET 2
#define R300_VPT_YSCALE 3
#define R300_VPT_YOFFSET 4
#define R300_VPT_ZSCALE 5
#define R300_VPT_ZOFFSET 6
#define R300_VPT_CMDSIZE 7
#define R600_VPT_CMD_0 0
#define R600_VPT_XSCALE 1
#define R600_VPT_XOFFSET 2
#define R600_VPT_YSCALE 3
#define R600_VPT_YOFFSET 4
#define R600_VPT_ZSCALE 5
#define R600_VPT_ZOFFSET 6
#define R600_VPT_CMDSIZE 7
#define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
#define R300_VIR_CNTL_0 1
#define R300_VIR_CNTL_1 2
#define R300_VIR_CNTL_2 3
#define R300_VIR_CNTL_3 4
#define R300_VIR_CNTL_4 5
#define R300_VIR_CNTL_5 6
#define R300_VIR_CNTL_6 7
#define R300_VIR_CNTL_7 8
#define R300_VIR_CMDSIZE 9
#define R600_VIR_CMD_0 0 /* vir is variable size (at least 1) */
#define R600_VIR_CNTL_0 1
#define R600_VIR_CNTL_1 2
#define R600_VIR_CNTL_2 3
#define R600_VIR_CNTL_3 4
#define R600_VIR_CNTL_4 5
#define R600_VIR_CNTL_5 6
#define R600_VIR_CNTL_6 7
#define R600_VIR_CNTL_7 8
#define R600_VIR_CMDSIZE 9
#define R300_VIC_CMD_0 0
#define R300_VIC_CNTL_0 1
#define R300_VIC_CNTL_1 2
#define R300_VIC_CMDSIZE 3
#define R600_VIC_CMD_0 0
#define R600_VIC_CNTL_0 1
#define R600_VIC_CNTL_1 2
#define R600_VIC_CMDSIZE 3
#define R300_VOF_CMD_0 0
#define R300_VOF_CNTL_0 1
#define R300_VOF_CNTL_1 2
#define R300_VOF_CMDSIZE 3
#define R600_VOF_CMD_0 0
#define R600_VOF_CNTL_0 1
#define R600_VOF_CNTL_1 2
#define R600_VOF_CMDSIZE 3
#define R300_PVS_CMD_0 0
#define R300_PVS_CNTL_1 1
#define R300_PVS_CNTL_2 2
#define R300_PVS_CNTL_3 3
#define R300_PVS_CMDSIZE 4
#define R600_PVS_CMD_0 0
#define R600_PVS_CNTL_1 1
#define R600_PVS_CNTL_2 2
#define R600_PVS_CNTL_3 3
#define R600_PVS_CMDSIZE 4
#define R300_GB_MISC_CMD_0 0
#define R300_GB_MISC_MSPOS_0 1
#define R300_GB_MISC_MSPOS_1 2
#define R300_GB_MISC_TILE_CONFIG 3
#define R300_GB_MISC_SELECT 4
#define R300_GB_MISC_AA_CONFIG 5
#define R300_GB_MISC_CMDSIZE 6
#define R600_GB_MISC_CMD_0 0
#define R600_GB_MISC_MSPOS_0 1
#define R600_GB_MISC_MSPOS_1 2
#define R600_GB_MISC_TILE_CONFIG 3
#define R600_GB_MISC_SELECT 4
#define R600_GB_MISC_AA_CONFIG 5
#define R600_GB_MISC_CMDSIZE 6
#define R300_TXE_CMD_0 0
#define R300_TXE_ENABLE 1
#define R300_TXE_CMDSIZE 2
#define R600_TXE_CMD_0 0
#define R600_TXE_ENABLE 1
#define R600_TXE_CMDSIZE 2
#define R300_PS_CMD_0 0
#define R300_PS_POINTSIZE 1
#define R300_PS_CMDSIZE 2
#define R600_PS_CMD_0 0
#define R600_PS_POINTSIZE 1
#define R600_PS_CMDSIZE 2
#define R300_ZBS_CMD_0 0
#define R300_ZBS_T_FACTOR 1
#define R300_ZBS_T_CONSTANT 2
#define R300_ZBS_W_FACTOR 3
#define R300_ZBS_W_CONSTANT 4
#define R300_ZBS_CMDSIZE 5
#define R600_ZBS_CMD_0 0
#define R600_ZBS_T_FACTOR 1
#define R600_ZBS_T_CONSTANT 2
#define R600_ZBS_W_FACTOR 3
#define R600_ZBS_W_CONSTANT 4
#define R600_ZBS_CMDSIZE 5
#define R300_CUL_CMD_0 0
#define R300_CUL_CULL 1
#define R300_CUL_CMDSIZE 2
#define R600_CUL_CMD_0 0
#define R600_CUL_CULL 1
#define R600_CUL_CMDSIZE 2
#define R300_RC_CMD_0 0
#define R300_RC_CNTL_0 1
#define R300_RC_CNTL_1 2
#define R300_RC_CMDSIZE 3
#define R600_RC_CMD_0 0
#define R600_RC_CNTL_0 1
#define R600_RC_CNTL_1 2
#define R600_RC_CMDSIZE 3
#define R300_RI_CMD_0 0
#define R300_RI_INTERP_0 1
#define R300_RI_INTERP_1 2
#define R300_RI_INTERP_2 3
#define R300_RI_INTERP_3 4
#define R300_RI_INTERP_4 5
#define R300_RI_INTERP_5 6
#define R300_RI_INTERP_6 7
#define R300_RI_INTERP_7 8
#define R300_RI_CMDSIZE 9
#define R600_RI_CMD_0 0
#define R600_RI_INTERP_0 1
#define R600_RI_INTERP_1 2
#define R600_RI_INTERP_2 3
#define R600_RI_INTERP_3 4
#define R600_RI_INTERP_4 5
#define R600_RI_INTERP_5 6
#define R600_RI_INTERP_6 7
#define R600_RI_INTERP_7 8
#define R600_RI_CMDSIZE 9
#define R500_RI_CMDSIZE 17
#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
#define R300_RR_INST_0 1
#define R300_RR_INST_1 2
#define R300_RR_INST_2 3
#define R300_RR_INST_3 4
#define R300_RR_INST_4 5
#define R300_RR_INST_5 6
#define R300_RR_INST_6 7
#define R300_RR_INST_7 8
#define R300_RR_CMDSIZE 9
#define R600_RR_CMD_0 0 /* rr is variable size (at least 1) */
#define R600_RR_INST_0 1
#define R600_RR_INST_1 2
#define R600_RR_INST_2 3
#define R600_RR_INST_3 4
#define R600_RR_INST_4 5
#define R600_RR_INST_5 6
#define R600_RR_INST_6 7
#define R600_RR_INST_7 8
#define R600_RR_CMDSIZE 9
#define R300_FP_CMD_0 0
#define R300_FP_CNTL0 1
#define R300_FP_CNTL1 2
#define R300_FP_CNTL2 3
#define R300_FP_CMD_1 4
#define R300_FP_NODE0 5
#define R300_FP_NODE1 6
#define R300_FP_NODE2 7
#define R300_FP_NODE3 8
#define R300_FP_CMDSIZE 9
#define R600_FP_CMD_0 0
#define R600_FP_CNTL0 1
#define R600_FP_CNTL1 2
#define R600_FP_CNTL2 3
#define R600_FP_CMD_1 4
#define R600_FP_NODE0 5
#define R600_FP_NODE1 6
#define R600_FP_NODE2 7
#define R600_FP_NODE3 8
#define R600_FP_CMDSIZE 9
#define R500_FP_CMD_0 0
#define R500_FP_CNTL 1
@@ -202,107 +202,107 @@ struct r300_texture_state {
#define R500_FP_FC_CNTL 8
#define R500_FP_CMDSIZE 9
#define R300_FPT_CMD_0 0
#define R300_FPT_INSTR_0 1
#define R300_FPT_CMDSIZE 65
#define R600_FPT_CMD_0 0
#define R600_FPT_INSTR_0 1
#define R600_FPT_CMDSIZE 65
#define R300_FPI_CMD_0 0
#define R300_FPI_INSTR_0 1
#define R300_FPI_CMDSIZE 65
#define R600_FPI_CMD_0 0
#define R600_FPI_INSTR_0 1
#define R600_FPI_CMDSIZE 65
/* R500 has space for 512 instructions - 6 dwords per instruction */
#define R500_FPI_CMDSIZE (512*6+1)
#define R300_FPP_CMD_0 0
#define R300_FPP_PARAM_0 1
#define R300_FPP_CMDSIZE (32*4+1)
#define R600_FPP_CMD_0 0
#define R600_FPP_PARAM_0 1
#define R600_FPP_CMDSIZE (32*4+1)
/* R500 has spcae for 256 constants - 4 dwords per constant */
#define R500_FPP_CMDSIZE (256*4+1)
#define R300_FOGS_CMD_0 0
#define R300_FOGS_STATE 1
#define R300_FOGS_CMDSIZE 2
#define R600_FOGS_CMD_0 0
#define R600_FOGS_STATE 1
#define R600_FOGS_CMDSIZE 2
#define R300_FOGC_CMD_0 0
#define R300_FOGC_R 1
#define R300_FOGC_G 2
#define R300_FOGC_B 3
#define R300_FOGC_CMDSIZE 4
#define R600_FOGC_CMD_0 0
#define R600_FOGC_R 1
#define R600_FOGC_G 2
#define R600_FOGC_B 3
#define R600_FOGC_CMDSIZE 4
#define R300_FOGP_CMD_0 0
#define R300_FOGP_SCALE 1
#define R300_FOGP_START 2
#define R300_FOGP_CMDSIZE 3
#define R600_FOGP_CMD_0 0
#define R600_FOGP_SCALE 1
#define R600_FOGP_START 2
#define R600_FOGP_CMDSIZE 3
#define R300_AT_CMD_0 0
#define R300_AT_ALPHA_TEST 1
#define R300_AT_UNKNOWN 2
#define R300_AT_CMDSIZE 3
#define R600_AT_CMD_0 0
#define R600_AT_ALPHA_TEST 1
#define R600_AT_UNKNOWN 2
#define R600_AT_CMDSIZE 3
#define R300_BLD_CMD_0 0
#define R300_BLD_CBLEND 1
#define R300_BLD_ABLEND 2
#define R300_BLD_CMDSIZE 3
#define R600_BLD_CMD_0 0
#define R600_BLD_CBLEND 1
#define R600_BLD_ABLEND 2
#define R600_BLD_CMDSIZE 3
#define R300_CMK_CMD_0 0
#define R300_CMK_COLORMASK 1
#define R300_CMK_CMDSIZE 2
#define R600_CMK_CMD_0 0
#define R600_CMK_COLORMASK 1
#define R600_CMK_CMDSIZE 2
#define R300_CB_CMD_0 0
#define R300_CB_OFFSET 1
#define R300_CB_CMD_1 2
#define R300_CB_PITCH 3
#define R300_CB_CMDSIZE 4
#define R600_CB_CMD_0 0
#define R600_CB_OFFSET 1
#define R600_CB_CMD_1 2
#define R600_CB_PITCH 3
#define R600_CB_CMDSIZE 4
#define R300_ZS_CMD_0 0
#define R300_ZS_CNTL_0 1
#define R300_ZS_CNTL_1 2
#define R300_ZS_CNTL_2 3
#define R300_ZS_CMDSIZE 4
#define R600_ZS_CMD_0 0
#define R600_ZS_CNTL_0 1
#define R600_ZS_CNTL_1 2
#define R600_ZS_CNTL_2 3
#define R600_ZS_CMDSIZE 4
#define R300_ZB_CMD_0 0
#define R300_ZB_OFFSET 1
#define R300_ZB_PITCH 2
#define R300_ZB_CMDSIZE 3
#define R600_ZB_CMD_0 0
#define R600_ZB_OFFSET 1
#define R600_ZB_PITCH 2
#define R600_ZB_CMDSIZE 3
#define R300_VAP_CNTL_FLUSH 0
#define R300_VAP_CNTL_FLUSH_1 1
#define R300_VAP_CNTL_CMD 2
#define R300_VAP_CNTL_INSTR 3
#define R300_VAP_CNTL_SIZE 4
#define R600_VAP_CNTL_FLUSH 0
#define R600_VAP_CNTL_FLUSH_1 1
#define R600_VAP_CNTL_CMD 2
#define R600_VAP_CNTL_INSTR 3
#define R600_VAP_CNTL_SIZE 4
#define R300_VPI_CMD_0 0
#define R300_VPI_INSTR_0 1
#define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
#define R600_VPI_CMD_0 0
#define R600_VPI_INSTR_0 1
#define R600_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
#define R300_VPP_CMD_0 0
#define R300_VPP_PARAM_0 1
#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
#define R600_VPP_CMD_0 0
#define R600_VPP_PARAM_0 1
#define R600_VPP_CMDSIZE 1025 /* 256 4-component parameters */
#define R300_VPUCP_CMD_0 0
#define R300_VPUCP_X 1
#define R300_VPUCP_Y 2
#define R300_VPUCP_Z 3
#define R300_VPUCP_W 4
#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
#define R600_VPUCP_CMD_0 0
#define R600_VPUCP_X 1
#define R600_VPUCP_Y 2
#define R600_VPUCP_Z 3
#define R600_VPUCP_W 4
#define R600_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
#define R300_VPS_CMD_0 0
#define R300_VPS_ZERO_0 1
#define R300_VPS_ZERO_1 2
#define R300_VPS_POINTSIZE 3
#define R300_VPS_ZERO_3 4
#define R300_VPS_CMDSIZE 5
#define R600_VPS_CMD_0 0
#define R600_VPS_ZERO_0 1
#define R600_VPS_ZERO_1 2
#define R600_VPS_POINTSIZE 3
#define R600_VPS_ZERO_3 4
#define R600_VPS_CMDSIZE 5
/* the layout is common for all fields inside tex */
#define R300_TEX_CMD_0 0
#define R300_TEX_VALUE_0 1
#define R600_TEX_CMD_0 0
#define R600_TEX_VALUE_0 1
/* We don't really use this, instead specify mtu+1 dynamically
#define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
#define R600_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
*/
/**
* Cache for hardware register state.
*/
struct r300_hw_state {
struct r600_hw_state {
struct radeon_state_atom vpt; /* viewport (1D98) */
struct radeon_state_atom vap_cntl;
struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
@@ -388,7 +388,7 @@ struct r300_hw_state {
} tex;
struct radeon_state_atom txe; /* tex enable (4104) */
radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
radeonTexObj *textures[R600_MAX_TEXTURE_UNITS];
};
/**
@@ -398,16 +398,16 @@ struct r300_hw_state {
/* Vertex shader state */
/* Perhaps more if we store programs in vmem? */
/* drm_r300_cmd_header_t->vpu->count is unsigned char */
/* drm_r600_cmd_header_t->vpu->count is unsigned char */
#define VSF_MAX_FRAGMENT_LENGTH (255*4)
/* Can be tested with colormat currently. */
#define VSF_MAX_FRAGMENT_TEMPS (14)
#define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
#define STATE_R300_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
#define STATE_R600_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
#define STATE_R600_TEXRECT_FACTOR (STATE_INTERNAL_DRIVER+1)
struct r300_vertex_shader_fragment {
struct r600_vertex_shader_fragment {
int length;
union {
GLuint d[VSF_MAX_FRAGMENT_LENGTH];
@@ -416,39 +416,39 @@ struct r300_vertex_shader_fragment {
} body;
};
struct r300_vertex_shader_state {
struct r300_vertex_shader_fragment program;
struct r600_vertex_shader_state {
struct r600_vertex_shader_fragment program;
};
extern int hw_tcl_on;
#define COLOR_IS_RGBA
#define TAG(x) r300##x
#define TAG(x) r600##x
#include "tnl_dd/t_dd_vertex.h"
#undef TAG
//#define CURRENT_VERTEX_SHADER(ctx) (ctx->VertexProgram._Current)
#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->selected_vp)
#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->selected_vp)
/* Should but doesnt work */
//#define CURRENT_VERTEX_SHADER(ctx) (R300_CONTEXT(ctx)->curr_vp)
//#define CURRENT_VERTEX_SHADER(ctx) (R600_CONTEXT(ctx)->curr_vp)
/* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
/* r600_vertex_shader_state and r600_vertex_program should probably be merged together someday.
* Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
*/
struct r300_vertex_program_key {
struct r600_vertex_program_key {
GLuint InputsRead;
GLuint OutputsWritten;
GLuint OutputsAdded;
};
struct r300_vertex_program {
struct r300_vertex_program *next;
struct r300_vertex_program_key key;
struct r600_vertex_program {
struct r600_vertex_program *next;
struct r600_vertex_program_key key;
int translated;
struct r300_vertex_shader_fragment program;
struct r600_vertex_shader_fragment program;
int pos_end;
int num_temporaries; /* Number of temp vars used by program */
@@ -460,10 +460,10 @@ struct r300_vertex_program {
int use_ref_count;
};
struct r300_vertex_program_cont {
struct r600_vertex_program_cont {
struct gl_vertex_program mesa_program; /* Must be first */
struct r300_vertex_shader_fragment params;
struct r300_vertex_program *progs;
struct r600_vertex_shader_fragment params;
struct r600_vertex_program *progs;
};
#define PFS_MAX_ALU_INST 64
@@ -472,13 +472,13 @@ struct r300_vertex_program_cont {
#define PFS_NUM_TEMP_REGS 32
#define PFS_NUM_CONST_REGS 16
struct r300_pfs_compile_state;
struct r600_pfs_compile_state;
/**
* Stores state that influences the compilation of a fragment program.
*/
struct r300_fragment_program_external_state {
struct r600_fragment_program_external_state {
struct {
/**
* If the sampler is used as a shadow sampler,
@@ -502,7 +502,7 @@ struct r300_fragment_program_external_state {
};
struct r300_fragment_program_node {
struct r600_fragment_program_node {
int tex_offset; /**< first tex instruction */
int tex_end; /**< last tex instruction, relative to tex_offset */
int alu_offset; /**< first ALU instruction */
@@ -511,9 +511,9 @@ struct r300_fragment_program_node {
};
/**
* Stores an R300 fragment program in its compiled-to-hardware form.
* Stores an R600 fragment program in its compiled-to-hardware form.
*/
struct r300_fragment_program_code {
struct r600_fragment_program_code {
struct {
int length; /**< total # of texture instructions used */
GLuint inst[PFS_MAX_TEX_INST];
@@ -529,7 +529,7 @@ struct r300_fragment_program_code {
} inst[PFS_MAX_ALU_INST];
} alu;
struct r300_fragment_program_node node[4];
struct r600_fragment_program_node node[4];
int cur_node;
int first_node_has_tex;
@@ -547,14 +547,14 @@ struct r300_fragment_program_code {
* Store everything about a fragment program that is needed
* to render with that program.
*/
struct r300_fragment_program {
struct r600_fragment_program {
struct gl_fragment_program mesa_program;
GLboolean translated;
GLboolean error;
struct r300_fragment_program_external_state state;
struct r300_fragment_program_code code;
struct r600_fragment_program_external_state state;
struct r600_fragment_program_code code;
GLboolean WritesDepth;
GLuint optimization;
@@ -623,30 +623,30 @@ struct r500_fragment_program {
GLuint optimization;
};
#define R300_MAX_AOS_ARRAYS 16
#define R600_MAX_AOS_ARRAYS 16
#define REG_COORDS 0
#define REG_COLOR0 1
#define REG_TEX0 2
struct r300_state {
struct r300_texture_state texture;
struct r600_state {
struct r600_texture_state texture;
int sw_tcl_inputs[VERT_ATTRIB_MAX];
struct r300_vertex_shader_state vertex_shader;
struct r600_vertex_shader_state vertex_shader;
DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R300 was configured for.
DECLARE_RENDERINPUTS(render_inputs_bitset); /* actual render inputs that R600 was configured for.
They are the same as tnl->render_inputs for fixed pipeline */
};
#define R300_FALLBACK_NONE 0
#define R300_FALLBACK_TCL 1
#define R300_FALLBACK_RAST 2
#define R600_FALLBACK_NONE 0
#define R600_FALLBACK_TCL 1
#define R600_FALLBACK_RAST 2
/* r300_swtcl.c
/* r600_swtcl.c
*/
struct r300_swtcl_info {
struct r600_swtcl_info {
/*
* Offset of the 4UB color data within a hardware (swtcl) vertex.
*/
@@ -670,16 +670,16 @@ struct r300_swtcl_info {
/**
* \brief R300 context structure.
* \brief R600 context structure.
*/
struct r300_context {
struct r600_context {
struct radeon_context radeon; /* parent class, must be first */
struct r300_hw_state hw;
struct r600_hw_state hw;
struct r300_state state;
struct r600_state state;
struct gl_vertex_program *curr_vp;
struct r300_vertex_program *selected_vp;
struct r600_vertex_program *selected_vp;
/* Vertex buffers
*/
@@ -688,21 +688,21 @@ struct r300_context {
GLboolean disable_lowimpact_fallback;
struct r300_swtcl_info swtcl;
struct r600_swtcl_info swtcl;
GLboolean vap_flush_needed;
};
#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
#define R600_CONTEXT(ctx) ((r600ContextPtr)(ctx->DriverCtx))
extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
extern void r600DestroyContext(__DRIcontextPrivate * driContextPriv);
extern GLboolean r600CreateContext(const __GLcontextModes * glVisual,
__DRIcontextPrivate * driContextPriv,
void *sharedContextPrivate);
extern void r300SelectVertexShader(r300ContextPtr r300);
extern void r300InitShaderFuncs(struct dd_function_table *functions);
extern int r300VertexProgUpdateParams(GLcontext * ctx,
struct r300_vertex_program_cont *vp,
extern void r600SelectVertexShader(r600ContextPtr r600);
extern void r600InitShaderFuncs(struct dd_function_table *functions);
extern int r600VertexProgUpdateParams(GLcontext * ctx,
struct r600_vertex_program_cont *vp,
float *dst);
#define RADEON_D_CAPTURE 0
@@ -710,7 +710,7 @@ extern int r300VertexProgUpdateParams(GLcontext * ctx,
#define RADEON_D_PLAYBACK_RAW 2
#define RADEON_D_T 3
#define r300PackFloat32 radeonPackFloat32
#define r300PackFloat24 radeonPackFloat24
#define r600PackFloat32 radeonPackFloat32
#define r600PackFloat24 radeonPackFloat24
#endif /* __R300_CONTEXT_H__ */
#endif /* __R600_CONTEXT_H__ */
src/mesa/drivers/dri/r600/r600_emit.c
+73 -73
View File
@@ -51,21 +51,21 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r600_ioctl.h"
#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \
SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \
SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \
SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \
SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \
SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE
#if SWIZZLE_X != R600_INPUT_ROUTE_SELECT_X || \
SWIZZLE_Y != R600_INPUT_ROUTE_SELECT_Y || \
SWIZZLE_Z != R600_INPUT_ROUTE_SELECT_Z || \
SWIZZLE_W != R600_INPUT_ROUTE_SELECT_W || \
SWIZZLE_ZERO != R600_INPUT_ROUTE_SELECT_ZERO || \
SWIZZLE_ONE != R600_INPUT_ROUTE_SELECT_ONE
#error Cannot change these!
#endif
#define DEBUG_ALL DEBUG_VERTS
#define DW_SIZE(x) ((inputs[tab[(x)]] << R300_DST_VEC_LOC_SHIFT) | \
(attribptr[tab[(x)]]->size - 1) << R300_DATA_TYPE_0_SHIFT)
#define DW_SIZE(x) ((inputs[tab[(x)]] << R600_DST_VEC_LOC_SHIFT) | \
(attribptr[tab[(x)]]->size - 1) << R600_DATA_TYPE_0_SHIFT)
GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
int *inputs, GLint * tab, GLuint nr)
{
GLuint i, dw;
@@ -74,15 +74,15 @@ GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
for (i = 0; i < nr; i += 2) {
/* make sure input is valid, would lockup the gpu */
assert(inputs[tab[i]] != -1);
dw = (R300_SIGNED | DW_SIZE(i));
dw = (R600_SIGNED | DW_SIZE(i));
if (i + 1 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
dw |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT;
} else {
assert(inputs[tab[i + 1]] != -1);
dw |= (R300_SIGNED |
DW_SIZE(i + 1)) << R300_DATA_TYPE_1_SHIFT;
dw |= (R600_SIGNED |
DW_SIZE(i + 1)) << R600_DATA_TYPE_1_SHIFT;
if (i + 2 == nr) {
dw |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
dw |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT;
}
}
dst[i >> 1] = dw;
@@ -91,26 +91,26 @@ GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
return (nr + 1) >> 1;
}
static GLuint r300VAPInputRoute1Swizzle(int swizzle[4])
static GLuint r600VAPInputRoute1Swizzle(int swizzle[4])
{
return (swizzle[0] << R300_SWIZZLE_SELECT_X_SHIFT) |
(swizzle[1] << R300_SWIZZLE_SELECT_Y_SHIFT) |
(swizzle[2] << R300_SWIZZLE_SELECT_Z_SHIFT) |
(swizzle[3] << R300_SWIZZLE_SELECT_W_SHIFT);
return (swizzle[0] << R600_SWIZZLE_SELECT_X_SHIFT) |
(swizzle[1] << R600_SWIZZLE_SELECT_Y_SHIFT) |
(swizzle[2] << R600_SWIZZLE_SELECT_Z_SHIFT) |
(swizzle[3] << R600_SWIZZLE_SELECT_W_SHIFT);
}
GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
{
GLuint i, dw;
for (i = 0; i < nr; i += 2) {
dw = (r300VAPInputRoute1Swizzle(swizzle[i]) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y |
R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT;
dw = (r600VAPInputRoute1Swizzle(swizzle[i]) |
((R600_WRITE_ENA_X | R600_WRITE_ENA_Y |
R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE0_SHIFT;
if (i + 1 < nr) {
dw |= (r300VAPInputRoute1Swizzle(swizzle[i + 1]) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y |
R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT;
dw |= (r600VAPInputRoute1Swizzle(swizzle[i + 1]) |
((R600_WRITE_ENA_X | R600_WRITE_ENA_Y |
R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT;
}
dst[i >> 1] = dw;
}
@@ -118,64 +118,64 @@ GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr)
return (nr + 1) >> 1;
}
GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead)
GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead)
{
/* No idea what this value means. I have seen other values written to
* this register... */
return 0x5555;
}
GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLuint i, vic_1 = 0;
if (InputsRead & (1 << VERT_ATTRIB_POS))
vic_1 |= R300_INPUT_CNTL_POS;
vic_1 |= R600_INPUT_CNTL_POS;
if (InputsRead & (1 << VERT_ATTRIB_NORMAL))
vic_1 |= R300_INPUT_CNTL_NORMAL;
vic_1 |= R600_INPUT_CNTL_NORMAL;
if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
vic_1 |= R300_INPUT_CNTL_COLOR;
vic_1 |= R600_INPUT_CNTL_COLOR;
rmesa->state.texture.tc_count = 0;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
rmesa->state.texture.tc_count++;
vic_1 |= R300_INPUT_CNTL_TC0 << i;
vic_1 |= R600_INPUT_CNTL_TC0 << i;
}
return vic_1;
}
GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten)
GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten)
{
GLuint ret = 0;
if (OutputsWritten & (1 << VERT_RESULT_HPOS))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
ret |= R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_COL0))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT;
ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_COL1))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
ret |= R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_BFC0)
|| OutputsWritten & (1 << VERT_RESULT_BFC1))
ret |=
R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT |
R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT |
R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
R600_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT |
R600_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT |
R600_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
if (OutputsWritten & (1 << VERT_RESULT_PSIZ))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
ret |= R600_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
return ret;
}
GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten)
GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten)
{
GLuint i, ret = 0, first_free_texcoord = 0;
@@ -199,11 +199,11 @@ GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten)
/* Emit vertex data to GART memory
* Route inputs to the vertex processor
* This function should never return R300_FALLBACK_TCL when using software tcl.
* This function should never return R600_FALLBACK_TCL when using software tcl.
*/
int r300EmitArrays(GLcontext * ctx)
int r600EmitArrays(GLcontext * ctx)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
GLuint nr;
@@ -214,8 +214,8 @@ int r300EmitArrays(GLcontext * ctx)
int vir_inputs[VERT_ATTRIB_MAX];
GLint tab[VERT_ATTRIB_MAX];
int swizzle[VERT_ATTRIB_MAX][4];
struct r300_vertex_program *prog =
(struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
struct r600_vertex_program *prog =
(struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
if (hw_tcl_on) {
inputs = prog->inputs;
@@ -287,8 +287,8 @@ int r300EmitArrays(GLcontext * ctx)
}
}
if (nr > R300_MAX_AOS_ARRAYS) {
return R300_FALLBACK_TCL;
if (nr > R600_MAX_AOS_ARRAYS) {
return R600_FALLBACK_TCL;
}
for (i = 0; i < nr; i++) {
@@ -310,55 +310,55 @@ int r300EmitArrays(GLcontext * ctx)
/* Setup INPUT_ROUTE. */
if (rmesa->radeon.radeonScreen->kernel_mm) {
R300_STATECHANGE(rmesa, vir[0]);
R600_STATECHANGE(rmesa, vir[0]);
rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF;
rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF;
rmesa->hw.vir[0].cmd[0] |=
(r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0],
(r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0],
vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16;
R300_STATECHANGE(rmesa, vir[1]);
R600_STATECHANGE(rmesa, vir[1]);
rmesa->hw.vir[1].cmd[0] |=
(r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
(r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle,
nr) & 0x3FFF) << 16;
} else {
R300_STATECHANGE(rmesa, vir[0]);
R600_STATECHANGE(rmesa, vir[0]);
((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count =
r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0],
r600VAPInputRoute0(&rmesa->hw.vir[0].cmd[R600_VIR_CNTL_0],
vb->AttribPtr, inputs, tab, nr);
R300_STATECHANGE(rmesa, vir[1]);
R600_STATECHANGE(rmesa, vir[1]);
((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count =
r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
r600VAPInputRoute1(&rmesa->hw.vir[1].cmd[R600_VIR_CNTL_0], swizzle,
nr);
}
/* Setup INPUT_CNTL. */
R300_STATECHANGE(rmesa, vic);
rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead);
R600_STATECHANGE(rmesa, vic);
rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead);
rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead);
/* Setup OUTPUT_VTX_FMT. */
R300_STATECHANGE(rmesa, vof);
rmesa->hw.vof.cmd[R300_VOF_CNTL_0] =
r300VAPOutputCntl0(ctx, OutputsWritten);
rmesa->hw.vof.cmd[R300_VOF_CNTL_1] =
r300VAPOutputCntl1(ctx, OutputsWritten);
R600_STATECHANGE(rmesa, vof);
rmesa->hw.vof.cmd[R600_VOF_CNTL_0] =
r600VAPOutputCntl0(ctx, OutputsWritten);
rmesa->hw.vof.cmd[R600_VOF_CNTL_1] =
r600VAPOutputCntl1(ctx, OutputsWritten);
rmesa->radeon.tcl.aos_count = nr;
return R300_FALLBACK_NONE;
return R600_FALLBACK_NONE;
}
void r300EmitCacheFlush(r300ContextPtr rmesa)
void r600EmitCacheFlush(r600ContextPtr rmesa)
{
BATCH_LOCALS(&rmesa->radeon);
BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT,
R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT,
R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
OUT_BATCH_REGVAL(R600_RB3D_DSTCACHE_CTLSTAT,
R600_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
R600_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(R600_ZB_ZCACHE_CTLSTAT,
R600_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
R600_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
END_BATCH();
COMMIT_BATCH();
}
src/mesa/drivers/dri/r600/r600_emit.h
+12 -12
View File
@@ -34,7 +34,7 @@
* Jerome Glisse <j.glisse@gmail.com>
*/
/* This files defines functions for accessing R300 hardware.
/* This files defines functions for accessing R600 hardware.
*/
#ifndef __R600_EMIT_H__
#define __R600_EMIT_H__
@@ -165,7 +165,7 @@ void static INLINE end_3d(radeonContextPtr radeon)
}
}
void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
void static INLINE cp_delay(r600ContextPtr rmesa, unsigned short count)
{
BATCH_LOCALS(&rmesa->radeon);
@@ -216,19 +216,19 @@ void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags)
}
}
extern int r300EmitArrays(GLcontext * ctx);
extern int r600EmitArrays(GLcontext * ctx);
extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
extern int r600PrimitiveType(r600ContextPtr rmesa, int prim);
extern int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim);
extern void r300EmitCacheFlush(r300ContextPtr rmesa);
extern void r600EmitCacheFlush(r600ContextPtr rmesa);
extern GLuint r300VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
extern GLuint r600VAPInputRoute0(uint32_t * dst, GLvector4f ** attribptr,
int *inputs, GLint * tab, GLuint nr);
extern GLuint r300VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
extern GLuint r300VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
extern GLuint r300VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
extern GLuint r300VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
extern GLuint r300VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
extern GLuint r600VAPInputRoute1(uint32_t * dst, int swizzle[][4], GLuint nr);
extern GLuint r600VAPInputCntl0(GLcontext * ctx, GLuint InputsRead);
extern GLuint r600VAPInputCntl1(GLcontext * ctx, GLuint InputsRead);
extern GLuint r600VAPOutputCntl0(GLcontext * ctx, GLuint OutputsWritten);
extern GLuint r600VAPOutputCntl1(GLcontext * ctx, GLuint OutputsWritten);
#endif
src/mesa/drivers/dri/r600/r600_fragprog.c
+56 -56
View File
@@ -85,8 +85,8 @@ static GLboolean transform_TEX(
struct radeon_transform_context *t,
struct prog_instruction* orig_inst, void* data)
{
struct r300_fragment_program_compiler *compiler =
(struct r300_fragment_program_compiler*)data;
struct r600_fragment_program_compiler *compiler =
(struct r600_fragment_program_compiler*)data;
struct prog_instruction inst = *orig_inst;
struct prog_instruction* tgt;
GLboolean destredirect = GL_FALSE;
@@ -127,7 +127,7 @@ static GLboolean transform_TEX(
*/
if (inst.Opcode != OPCODE_KIL && inst.TexSrcTarget == TEXTURE_RECT_INDEX) {
gl_state_index tokens[STATE_LENGTH] = {
STATE_INTERNAL, STATE_R300_TEXRECT_FACTOR, 0, 0,
STATE_INTERNAL, STATE_R600_TEXRECT_FACTOR, 0, 0,
0
};
@@ -247,13 +247,13 @@ static GLboolean transform_TEX(
}
static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp)
static void update_params(r600ContextPtr r600, struct r600_fragment_program *fp)
{
struct gl_fragment_program *mp = &fp->mesa_program;
/* Ask Mesa nicely to fill in ParameterValues for us */
if (mp->Base.Parameters)
_mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters);
_mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters);
}
@@ -268,7 +268,7 @@ static void update_params(r300ContextPtr r300, struct r300_fragment_program *fp)
* \todo if/when r5xx supports the radeon_program architecture, this is a
* likely candidate for code sharing.
*/
static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler)
static void insert_WPOS_trailer(struct r600_fragment_program_compiler *compiler)
{
GLuint InputsRead = compiler->fp->mesa_program.Base.InputsRead;
@@ -276,7 +276,7 @@ static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler)
return;
static gl_state_index tokens[STATE_LENGTH] = {
STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0
STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0
};
struct prog_instruction *fpi;
GLuint window_index;
@@ -382,9 +382,9 @@ static GLuint build_func(GLuint comparefunc)
* fragment program.
*/
static void build_state(
r300ContextPtr r300,
struct r300_fragment_program *fp,
struct r300_fragment_program_external_state *state)
r600ContextPtr r600,
struct r600_fragment_program *fp,
struct r600_fragment_program_external_state *state)
{
int unit;
@@ -392,7 +392,7 @@ static void build_state(
for(unit = 0; unit < 16; ++unit) {
if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current;
state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
@@ -401,12 +401,12 @@ static void build_state(
}
void r300TranslateFragmentShader(r300ContextPtr r300,
struct r300_fragment_program *fp)
void r600TranslateFragmentShader(r600ContextPtr r600,
struct r600_fragment_program *fp)
{
struct r300_fragment_program_external_state state;
struct r600_fragment_program_external_state state;
build_state(r300, fp, &state);
build_state(r600, fp, &state);
if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
/* TODO: cache compiled programs */
fp->translated = GL_FALSE;
@@ -414,12 +414,12 @@ void r300TranslateFragmentShader(r300ContextPtr r300,
}
if (!fp->translated) {
struct r300_fragment_program_compiler compiler;
struct r600_fragment_program_compiler compiler;
compiler.r300 = r300;
compiler.r600 = r600;
compiler.fp = fp;
compiler.code = &fp->code;
compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base);
compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Fragment Program: Initial program:\n");
@@ -434,7 +434,7 @@ void r300TranslateFragmentShader(r300ContextPtr r300,
{ &radeonTransformTrigSimple, 0 }
};
radeonLocalTransform(
r300->radeon.glCtx,
r600->radeon.glCtx,
compiler.program,
3, transformations);
@@ -445,18 +445,18 @@ void r300TranslateFragmentShader(r300ContextPtr r300,
struct radeon_nqssadce_descr nqssadce = {
.Init = &nqssadce_init,
.IsNativeSwizzle = &r300FPIsNativeSwizzle,
.BuildSwizzle = &r300FPBuildSwizzle,
.IsNativeSwizzle = &r600FPIsNativeSwizzle,
.BuildSwizzle = &r600FPBuildSwizzle,
.RewriteDepthOut = GL_TRUE
};
radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce);
radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: after NqSSA-DCE:\n");
_mesa_print_program(compiler.program);
}
if (!r300FragmentProgramEmit(&compiler))
if (!r600FragmentProgramEmit(&compiler))
fp->error = GL_TRUE;
/* Subtle: Rescue any parameters that have been added during transformations */
@@ -464,22 +464,22 @@ void r300TranslateFragmentShader(r300ContextPtr r300,
fp->mesa_program.Base.Parameters = compiler.program->Parameters;
compiler.program->Parameters = 0;
_mesa_reference_program(r300->radeon.glCtx, &compiler.program, NULL);
_mesa_reference_program(r600->radeon.glCtx, &compiler.program, NULL);
if (!fp->error)
fp->translated = GL_TRUE;
if (fp->error || (RADEON_DEBUG & DEBUG_PIXEL))
r300FragmentProgramDump(fp, &fp->code);
r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM);
r600FragmentProgramDump(fp, &fp->code);
r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM);
}
update_params(r300, fp);
update_params(r600, fp);
}
/* just some random things... */
void r300FragmentProgramDump(
struct r300_fragment_program *fp,
struct r300_fragment_program_code *code)
void r600FragmentProgramDump(
struct r600_fragment_program *fp,
struct r600_fragment_program_code *code)
{
int n, i, j;
static int pc = 0;
@@ -505,18 +505,18 @@ void r300FragmentProgramDump(
const char *instr;
switch ((code->tex.
inst[i] >> R300_TEX_INST_SHIFT) &
inst[i] >> R600_TEX_INST_SHIFT) &
15) {
case R300_TEX_OP_LD:
case R600_TEX_OP_LD:
instr = "TEX";
break;
case R300_TEX_OP_KIL:
case R600_TEX_OP_KIL:
instr = "KIL";
break;
case R300_TEX_OP_TXP:
case R600_TEX_OP_TXP:
instr = "TXP";
break;
case R300_TEX_OP_TXB:
case R600_TEX_OP_TXB:
instr = "TXB";
break;
default:
@@ -527,13 +527,13 @@ void r300FragmentProgramDump(
" %s t%i, %c%i, texture[%i] (%08x)\n",
instr,
(code->tex.
inst[i] >> R300_DST_ADDR_SHIFT) & 31,
inst[i] >> R600_DST_ADDR_SHIFT) & 31,
't',
(code->tex.
inst[i] >> R300_SRC_ADDR_SHIFT) & 31,
inst[i] >> R600_SRC_ADDR_SHIFT) & 31,
(code->tex.
inst[i] & R300_TEX_ID_MASK) >>
R300_TEX_ID_SHIFT,
inst[i] & R600_TEX_ID_MASK) >>
R600_TEX_ID_SHIFT,
code->tex.inst[i]);
}
}
@@ -559,45 +559,45 @@ void r300FragmentProgramDump(
dstc[0] = 0;
sprintf(flags, "%s%s%s",
(code->alu.inst[i].
inst1 & R300_ALU_DSTC_REG_X) ? "x" : "",
inst1 & R600_ALU_DSTC_REG_X) ? "x" : "",
(code->alu.inst[i].
inst1 & R300_ALU_DSTC_REG_Y) ? "y" : "",
inst1 & R600_ALU_DSTC_REG_Y) ? "y" : "",
(code->alu.inst[i].
inst1 & R300_ALU_DSTC_REG_Z) ? "z" : "");
inst1 & R600_ALU_DSTC_REG_Z) ? "z" : "");
if (flags[0] != 0) {
sprintf(dstc, "t%i.%s ",
(code->alu.inst[i].
inst1 >> R300_ALU_DSTC_SHIFT) & 31,
inst1 >> R600_ALU_DSTC_SHIFT) & 31,
flags);
}
sprintf(flags, "%s%s%s",
(code->alu.inst[i].
inst1 & R300_ALU_DSTC_OUTPUT_X) ? "x" : "",
inst1 & R600_ALU_DSTC_OUTPUT_X) ? "x" : "",
(code->alu.inst[i].
inst1 & R300_ALU_DSTC_OUTPUT_Y) ? "y" : "",
inst1 & R600_ALU_DSTC_OUTPUT_Y) ? "y" : "",
(code->alu.inst[i].
inst1 & R300_ALU_DSTC_OUTPUT_Z) ? "z" : "");
inst1 & R600_ALU_DSTC_OUTPUT_Z) ? "z" : "");
if (flags[0] != 0) {
sprintf(tmp, "o%i.%s",
(code->alu.inst[i].
inst1 >> R300_ALU_DSTC_SHIFT) & 31,
inst1 >> R600_ALU_DSTC_SHIFT) & 31,
flags);
strcat(dstc, tmp);
}
dsta[0] = 0;
if (code->alu.inst[i].inst3 & R300_ALU_DSTA_REG) {
if (code->alu.inst[i].inst3 & R600_ALU_DSTA_REG) {
sprintf(dsta, "t%i.w ",
(code->alu.inst[i].
inst3 >> R300_ALU_DSTA_SHIFT) & 31);
inst3 >> R600_ALU_DSTA_SHIFT) & 31);
}
if (code->alu.inst[i].inst3 & R300_ALU_DSTA_OUTPUT) {
if (code->alu.inst[i].inst3 & R600_ALU_DSTA_OUTPUT) {
sprintf(tmp, "o%i.w ",
(code->alu.inst[i].
inst3 >> R300_ALU_DSTA_SHIFT) & 31);
inst3 >> R600_ALU_DSTA_SHIFT) & 31);
strcat(dsta, tmp);
}
if (code->alu.inst[i].inst3 & R300_ALU_DSTA_DEPTH) {
if (code->alu.inst[i].inst3 & R600_ALU_DSTA_DEPTH) {
strcat(dsta, "Z");
}
@@ -617,19 +617,19 @@ void r300FragmentProgramDump(
d = regc & 31;
if (d < 12) {
switch (d % 4) {
case R300_ALU_ARGC_SRC0C_XYZ:
case R600_ALU_ARGC_SRC0C_XYZ:
sprintf(buf, "%s.xyz",
srcc[d / 4]);
break;
case R300_ALU_ARGC_SRC0C_XXX:
case R600_ALU_ARGC_SRC0C_XXX:
sprintf(buf, "%s.xxx",
srcc[d / 4]);
break;
case R300_ALU_ARGC_SRC0C_YYY:
case R600_ALU_ARGC_SRC0C_YYY:
sprintf(buf, "%s.yyy",
srcc[d / 4]);
break;
case R300_ALU_ARGC_SRC0C_ZZZ:
case R600_ALU_ARGC_SRC0C_ZZZ:
sprintf(buf, "%s.zzz",
srcc[d / 4]);
break;
src/mesa/drivers/dri/r600/r600_fragprog.h
+30 -30
View File
@@ -66,67 +66,67 @@
#define FP_SELC_MASK_XYZ 7
#define FP_SELC(destidx,regmask,outmask,src0,src1,src2) \
(((destidx) << R300_ALU_DSTC_SHIFT) | \
(((destidx) << R600_ALU_DSTC_SHIFT) | \
(FP_SELC_MASK_##regmask << 23) | \
(FP_SELC_MASK_##outmask << 26) | \
((src0) << R300_ALU_SRC0C_SHIFT) | \
((src1) << R300_ALU_SRC1C_SHIFT) | \
((src2) << R300_ALU_SRC2C_SHIFT))
((src0) << R600_ALU_SRC0C_SHIFT) | \
((src1) << R600_ALU_SRC1C_SHIFT) | \
((src2) << R600_ALU_SRC2C_SHIFT))
#define FP_SELA_MASK_NO 0
#define FP_SELA_MASK_W 1
#define FP_SELA(destidx,regmask,outmask,src0,src1,src2) \
(((destidx) << R300_ALU_DSTA_SHIFT) | \
(((destidx) << R600_ALU_DSTA_SHIFT) | \
(FP_SELA_MASK_##regmask << 23) | \
(FP_SELA_MASK_##outmask << 24) | \
((src0) << R300_ALU_SRC0A_SHIFT) | \
((src1) << R300_ALU_SRC1A_SHIFT) | \
((src2) << R300_ALU_SRC2A_SHIFT))
((src0) << R600_ALU_SRC0A_SHIFT) | \
((src1) << R600_ALU_SRC1A_SHIFT) | \
((src2) << R600_ALU_SRC2A_SHIFT))
/* Produce unshifted argument selectors */
#define FP_ARGC(source) R300_ALU_ARGC_##source
#define FP_ARGA(source) R300_ALU_ARGA_##source
#define FP_ARGC(source) R600_ALU_ARGC_##source
#define FP_ARGA(source) R600_ALU_ARGA_##source
#define FP_ABS(arg) ((arg) | (1 << 6))
#define FP_NEG(arg) ((arg) ^ (1 << 5))
/* Produce instruction dword */
#define FP_INSTRC(opcode,arg0,arg1,arg2) \
(R300_ALU_OUTC_##opcode | \
((arg0) << R300_ALU_ARG0C_SHIFT) | \
((arg1) << R300_ALU_ARG1C_SHIFT) | \
((arg2) << R300_ALU_ARG2C_SHIFT))
(R600_ALU_OUTC_##opcode | \
((arg0) << R600_ALU_ARG0C_SHIFT) | \
((arg1) << R600_ALU_ARG1C_SHIFT) | \
((arg2) << R600_ALU_ARG2C_SHIFT))
#define FP_INSTRA(opcode,arg0,arg1,arg2) \
(R300_ALU_OUTA_##opcode | \
((arg0) << R300_ALU_ARG0A_SHIFT) | \
((arg1) << R300_ALU_ARG1A_SHIFT) | \
((arg2) << R300_ALU_ARG2A_SHIFT))
(R600_ALU_OUTA_##opcode | \
((arg0) << R600_ALU_ARG0A_SHIFT) | \
((arg1) << R600_ALU_ARG1A_SHIFT) | \
((arg2) << R600_ALU_ARG2A_SHIFT))
#endif
struct r300_fragment_program;
struct r600_fragment_program;
extern void r300TranslateFragmentShader(r300ContextPtr r300,
struct r300_fragment_program *fp);
extern void r600TranslateFragmentShader(r600ContextPtr r600,
struct r600_fragment_program *fp);
/**
* Used internally by the r300 fragment program code to store compile-time
* Used internally by the r600 fragment program code to store compile-time
* only data.
*/
struct r300_fragment_program_compiler {
r300ContextPtr r300;
struct r300_fragment_program *fp;
struct r300_fragment_program_code *code;
struct r600_fragment_program_compiler {
r600ContextPtr r600;
struct r600_fragment_program *fp;
struct r600_fragment_program_code *code;
struct gl_program *program;
};
extern GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler);
extern GLboolean r600FragmentProgramEmit(struct r600_fragment_program_compiler *compiler);
extern void r300FragmentProgramDump(
struct r300_fragment_program *fp,
struct r300_fragment_program_code *code);
extern void r600FragmentProgramDump(
struct r600_fragment_program *fp,
struct r600_fragment_program_code *code);
#endif
src/mesa/drivers/dri/r600/r600_fragprog_emit.c
+53 -53
View File
@@ -28,7 +28,7 @@
/**
* \file
*
* Emit the r300_fragment_program_code that can be understood by the hardware.
* Emit the r600_fragment_program_code that can be understood by the hardware.
* Input is a pre-transformed radeon_program.
*
* \author Ben Skeggs <darktama@iinet.net.au>
@@ -46,8 +46,8 @@
#define PROG_CODE \
struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)data; \
struct r300_fragment_program_code *code = c->code
struct r600_fragment_program_compiler *c = (struct r600_fragment_program_compiler*)data; \
struct r600_fragment_program_code *code = c->code
#define error(fmt, args...) do { \
fprintf(stderr, "%s::%s(): " fmt "\n", \
@@ -83,7 +83,7 @@ static GLboolean emit_const(void* data, GLuint file, GLuint index, GLuint *hwind
/**
* Mark a temporary register as used.
*/
static void use_temporary(struct r300_fragment_program_code *code, GLuint index)
static void use_temporary(struct r600_fragment_program_code *code, GLuint index)
{
if (index > code->max_temp_idx)
code->max_temp_idx = index;
@@ -93,41 +93,41 @@ static void use_temporary(struct r300_fragment_program_code *code, GLuint index)
static GLuint translate_rgb_opcode(GLuint opcode)
{
switch(opcode) {
case OPCODE_CMP: return R300_ALU_OUTC_CMP;
case OPCODE_DP3: return R300_ALU_OUTC_DP3;
case OPCODE_DP4: return R300_ALU_OUTC_DP4;
case OPCODE_FRC: return R300_ALU_OUTC_FRC;
case OPCODE_CMP: return R600_ALU_OUTC_CMP;
case OPCODE_DP3: return R600_ALU_OUTC_DP3;
case OPCODE_DP4: return R600_ALU_OUTC_DP4;
case OPCODE_FRC: return R600_ALU_OUTC_FRC;
default:
error("translate_rgb_opcode(%i): Unknown opcode", opcode);
/* fall through */
case OPCODE_NOP:
/* fall through */
case OPCODE_MAD: return R300_ALU_OUTC_MAD;
case OPCODE_MAX: return R300_ALU_OUTC_MAX;
case OPCODE_MIN: return R300_ALU_OUTC_MIN;
case OPCODE_REPL_ALPHA: return R300_ALU_OUTC_REPL_ALPHA;
case OPCODE_MAD: return R600_ALU_OUTC_MAD;
case OPCODE_MAX: return R600_ALU_OUTC_MAX;
case OPCODE_MIN: return R600_ALU_OUTC_MIN;
case OPCODE_REPL_ALPHA: return R600_ALU_OUTC_REPL_ALPHA;
}
}
static GLuint translate_alpha_opcode(GLuint opcode)
{
switch(opcode) {
case OPCODE_CMP: return R300_ALU_OUTA_CMP;
case OPCODE_DP3: return R300_ALU_OUTA_DP4;
case OPCODE_DP4: return R300_ALU_OUTA_DP4;
case OPCODE_EX2: return R300_ALU_OUTA_EX2;
case OPCODE_FRC: return R300_ALU_OUTA_FRC;
case OPCODE_LG2: return R300_ALU_OUTA_LG2;
case OPCODE_CMP: return R600_ALU_OUTA_CMP;
case OPCODE_DP3: return R600_ALU_OUTA_DP4;
case OPCODE_DP4: return R600_ALU_OUTA_DP4;
case OPCODE_EX2: return R600_ALU_OUTA_EX2;
case OPCODE_FRC: return R600_ALU_OUTA_FRC;
case OPCODE_LG2: return R600_ALU_OUTA_LG2;
default:
error("translate_rgb_opcode(%i): Unknown opcode", opcode);
/* fall through */
case OPCODE_NOP:
/* fall through */
case OPCODE_MAD: return R300_ALU_OUTA_MAD;
case OPCODE_MAX: return R300_ALU_OUTA_MAX;
case OPCODE_MIN: return R300_ALU_OUTA_MIN;
case OPCODE_RCP: return R300_ALU_OUTA_RCP;
case OPCODE_RSQ: return R300_ALU_OUTA_RSQ;
case OPCODE_MAD: return R600_ALU_OUTA_MAD;
case OPCODE_MAX: return R600_ALU_OUTA_MAX;
case OPCODE_MIN: return R600_ALU_OUTA_MIN;
case OPCODE_RCP: return R600_ALU_OUTA_RCP;
case OPCODE_RSQ: return R600_ALU_OUTA_RSQ;
}
}
@@ -161,46 +161,46 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst)
use_temporary(code, inst->Alpha.Src[j].Index);
code->alu.inst[ip].inst3 |= src << (6*j);
GLuint arg = r300FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle);
GLuint arg = r600FPTranslateRGBSwizzle(inst->RGB.Arg[j].Source, inst->RGB.Arg[j].Swizzle);
arg |= inst->RGB.Arg[j].Abs << 6;
arg |= inst->RGB.Arg[j].Negate << 5;
code->alu.inst[ip].inst0 |= arg << (7*j);
arg = r300FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle);
arg = r600FPTranslateAlphaSwizzle(inst->Alpha.Arg[j].Source, inst->Alpha.Arg[j].Swizzle);
arg |= inst->Alpha.Arg[j].Abs << 6;
arg |= inst->Alpha.Arg[j].Negate << 5;
code->alu.inst[ip].inst2 |= arg << (7*j);
}
if (inst->RGB.Saturate)
code->alu.inst[ip].inst0 |= R300_ALU_OUTC_CLAMP;
code->alu.inst[ip].inst0 |= R600_ALU_OUTC_CLAMP;
if (inst->Alpha.Saturate)
code->alu.inst[ip].inst2 |= R300_ALU_OUTA_CLAMP;
code->alu.inst[ip].inst2 |= R600_ALU_OUTA_CLAMP;
if (inst->RGB.WriteMask) {
use_temporary(code, inst->RGB.DestIndex);
code->alu.inst[ip].inst1 |=
(inst->RGB.DestIndex << R300_ALU_DSTC_SHIFT) |
(inst->RGB.WriteMask << R300_ALU_DSTC_REG_MASK_SHIFT);
(inst->RGB.DestIndex << R600_ALU_DSTC_SHIFT) |
(inst->RGB.WriteMask << R600_ALU_DSTC_REG_MASK_SHIFT);
}
if (inst->RGB.OutputWriteMask) {
code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R300_ALU_DSTC_OUTPUT_MASK_SHIFT);
code->node[code->cur_node].flags |= R300_RGBA_OUT;
code->alu.inst[ip].inst1 |= (inst->RGB.OutputWriteMask << R600_ALU_DSTC_OUTPUT_MASK_SHIFT);
code->node[code->cur_node].flags |= R600_RGBA_OUT;
}
if (inst->Alpha.WriteMask) {
use_temporary(code, inst->Alpha.DestIndex);
code->alu.inst[ip].inst3 |=
(inst->Alpha.DestIndex << R300_ALU_DSTA_SHIFT) |
R300_ALU_DSTA_REG;
(inst->Alpha.DestIndex << R600_ALU_DSTA_SHIFT) |
R600_ALU_DSTA_REG;
}
if (inst->Alpha.OutputWriteMask) {
code->alu.inst[ip].inst3 |= R300_ALU_DSTA_OUTPUT;
code->node[code->cur_node].flags |= R300_RGBA_OUT;
code->alu.inst[ip].inst3 |= R600_ALU_DSTA_OUTPUT;
code->node[code->cur_node].flags |= R600_RGBA_OUT;
}
if (inst->Alpha.DepthWriteMask) {
code->alu.inst[ip].inst3 |= R300_ALU_DSTA_DEPTH;
code->node[code->cur_node].flags |= R300_W_OUT;
code->alu.inst[ip].inst3 |= R600_ALU_DSTA_DEPTH;
code->node[code->cur_node].flags |= R600_W_OUT;
c->fp->WritesDepth = GL_TRUE;
}
@@ -211,10 +211,10 @@ static GLboolean emit_alu(void* data, struct radeon_pair_instruction* inst)
/**
* Finish the current node without advancing to the next one.
*/
static GLboolean finish_node(struct r300_fragment_program_compiler *c)
static GLboolean finish_node(struct r600_fragment_program_compiler *c)
{
struct r300_fragment_program_code *code = c->code;
struct r300_fragment_program_node *node = &code->node[code->cur_node];
struct r600_fragment_program_code *code = c->code;
struct r600_fragment_program_node *node = &code->node[code->cur_node];
if (node->alu_end < 0) {
/* Generate a single NOP for this node */
@@ -262,7 +262,7 @@ static GLboolean begin_tex(void* data)
if (!finish_node(c))
return GL_FALSE;
struct r300_fragment_program_node *node = &code->node[++code->cur_node];
struct r600_fragment_program_node *node = &code->node[++code->cur_node];
node->alu_offset = code->alu.length;
node->alu_end = -1;
node->tex_offset = code->tex.length;
@@ -285,10 +285,10 @@ static GLboolean emit_tex(void* data, struct prog_instruction* inst)
GLuint opcode;
switch(inst->Opcode) {
case OPCODE_KIL: opcode = R300_TEX_OP_KIL; break;
case OPCODE_TEX: opcode = R300_TEX_OP_LD; break;
case OPCODE_TXB: opcode = R300_TEX_OP_TXB; break;
case OPCODE_TXP: opcode = R300_TEX_OP_TXP; break;
case OPCODE_KIL: opcode = R600_TEX_OP_KIL; break;
case OPCODE_TEX: opcode = R600_TEX_OP_LD; break;
case OPCODE_TXB: opcode = R600_TEX_OP_TXB; break;
case OPCODE_TXP: opcode = R600_TEX_OP_TXP; break;
default:
error("Unknown texture opcode %i", inst->Opcode);
return GL_FALSE;
@@ -305,10 +305,10 @@ static GLboolean emit_tex(void* data, struct prog_instruction* inst)
code->node[code->cur_node].tex_end++;
code->tex.inst[code->tex.length++] =
(inst->SrcReg[0].Index << R300_SRC_ADDR_SHIFT) |
(dest << R300_DST_ADDR_SHIFT) |
(unit << R300_TEX_ID_SHIFT) |
(opcode << R300_TEX_INST_SHIFT);
(inst->SrcReg[0].Index << R600_SRC_ADDR_SHIFT) |
(dest << R600_DST_ADDR_SHIFT) |
(unit << R600_TEX_ID_SHIFT) |
(opcode << R600_TEX_INST_SHIFT);
return GL_TRUE;
}
@@ -325,15 +325,15 @@ static const struct radeon_pair_handler pair_handler = {
* Final compilation step: Turn the intermediate radeon_program into
* machine-readable instructions.
*/
GLboolean r300FragmentProgramEmit(struct r300_fragment_program_compiler *compiler)
GLboolean r600FragmentProgramEmit(struct r600_fragment_program_compiler *compiler)
{
struct r300_fragment_program_code *code = compiler->code;
struct r600_fragment_program_code *code = compiler->code;
_mesa_bzero(code, sizeof(struct r300_fragment_program_code));
_mesa_bzero(code, sizeof(struct r600_fragment_program_code));
code->node[0].alu_end = -1;
code->node[0].tex_end = -1;
if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler))
if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler))
return GL_FALSE;
if (!finish_node(compiler))
src/mesa/drivers/dri/r600/r600_fragprog_swizzle.c
+19 -19
View File
@@ -27,7 +27,7 @@
/**
* @file
* Utilities to deal with the somewhat odd restriction on R300 fragment
* Utilities to deal with the somewhat odd restriction on R600 fragment
* program swizzles.
*/
@@ -45,16 +45,16 @@ struct swizzle_data {
};
static const struct swizzle_data native_swizzles[] = {
{MAKE_SWZ3(X, Y, Z), R300_ALU_ARGC_SRC0C_XYZ, 4},
{MAKE_SWZ3(X, X, X), R300_ALU_ARGC_SRC0C_XXX, 4},
{MAKE_SWZ3(Y, Y, Y), R300_ALU_ARGC_SRC0C_YYY, 4},
{MAKE_SWZ3(Z, Z, Z), R300_ALU_ARGC_SRC0C_ZZZ, 4},
{MAKE_SWZ3(W, W, W), R300_ALU_ARGC_SRC0A, 1},
{MAKE_SWZ3(Y, Z, X), R300_ALU_ARGC_SRC0C_YZX, 1},
{MAKE_SWZ3(Z, X, Y), R300_ALU_ARGC_SRC0C_ZXY, 1},
{MAKE_SWZ3(W, Z, Y), R300_ALU_ARGC_SRC0CA_WZY, 1},
{MAKE_SWZ3(ONE, ONE, ONE), R300_ALU_ARGC_ONE, 0},
{MAKE_SWZ3(ZERO, ZERO, ZERO), R300_ALU_ARGC_ZERO, 0}
{MAKE_SWZ3(X, Y, Z), R600_ALU_ARGC_SRC0C_XYZ, 4},
{MAKE_SWZ3(X, X, X), R600_ALU_ARGC_SRC0C_XXX, 4},
{MAKE_SWZ3(Y, Y, Y), R600_ALU_ARGC_SRC0C_YYY, 4},
{MAKE_SWZ3(Z, Z, Z), R600_ALU_ARGC_SRC0C_ZZZ, 4},
{MAKE_SWZ3(W, W, W), R600_ALU_ARGC_SRC0A, 1},
{MAKE_SWZ3(Y, Z, X), R600_ALU_ARGC_SRC0C_YZX, 1},
{MAKE_SWZ3(Z, X, Y), R600_ALU_ARGC_SRC0C_ZXY, 1},
{MAKE_SWZ3(W, Z, Y), R600_ALU_ARGC_SRC0CA_WZY, 1},
{MAKE_SWZ3(ONE, ONE, ONE), R600_ALU_ARGC_ONE, 0},
{MAKE_SWZ3(ZERO, ZERO, ZERO), R600_ALU_ARGC_ZERO, 0}
};
static const int num_native_swizzles = sizeof(native_swizzles)/sizeof(native_swizzles[0]);
@@ -89,7 +89,7 @@ static const struct swizzle_data* lookup_native_swizzle(GLuint swizzle)
* Check whether the given instruction supports the swizzle and negate
* combinations in the given source register.
*/
GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg)
GLboolean r600FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg)
{
if (reg.Abs)
reg.NegateBase = 0;
@@ -134,7 +134,7 @@ GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg)
/**
* Generate MOV dst, src using only native swizzles.
*/
void r300FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src)
void r600FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst, struct prog_src_register src)
{
if (src.Abs)
src.NegateBase = 0;
@@ -196,7 +196,7 @@ void r300FPBuildSwizzle(struct nqssadce_state *s, struct prog_dst_register dst,
* Translate an RGB (XYZ) swizzle into the hardware code for the given
* instruction source.
*/
GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle)
GLuint r600FPTranslateRGBSwizzle(GLuint src, GLuint swizzle)
{
const struct swizzle_data* sd = lookup_native_swizzle(swizzle);
@@ -213,15 +213,15 @@ GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle)
* Translate an Alpha (W) swizzle into the hardware code for the given
* instruction source.
*/
GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle)
GLuint r600FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle)
{
if (swizzle < 3)
return swizzle + 3*src;
switch(swizzle) {
case SWIZZLE_W: return R300_ALU_ARGA_SRC0A + src;
case SWIZZLE_ONE: return R300_ALU_ARGA_ONE;
case SWIZZLE_ZERO: return R300_ALU_ARGA_ZERO;
default: return R300_ALU_ARGA_ONE;
case SWIZZLE_W: return R600_ALU_ARGA_SRC0A + src;
case SWIZZLE_ONE: return R600_ALU_ARGA_ONE;
case SWIZZLE_ZERO: return R600_ALU_ARGA_ZERO;
default: return R600_ALU_ARGA_ONE;
}
}
src/mesa/drivers/dri/r600/r600_fragprog_swizzle.h
+5 -5
View File
@@ -33,10 +33,10 @@
struct nqssadce_state;
GLboolean r300FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg);
void r300FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
GLboolean r600FPIsNativeSwizzle(GLuint opcode, struct prog_src_register reg);
void r600FPBuildSwizzle(struct nqssadce_state*, struct prog_dst_register dst, struct prog_src_register src);
GLuint r300FPTranslateRGBSwizzle(GLuint src, GLuint swizzle);
GLuint r300FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle);
GLuint r600FPTranslateRGBSwizzle(GLuint src, GLuint swizzle);
GLuint r600FPTranslateAlphaSwizzle(GLuint src, GLuint swizzle);
#endif /* __R300_FRAGPROG_SWIZZLE_H_ */
#endif /* __R600_FRAGPROG_SWIZZLE_H_ */
src/mesa/drivers/dri/r600/r600_ioctl.c
+185 -185
View File
@@ -66,22 +66,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define CLEARBUFFER_DEPTH 0x2
#define CLEARBUFFER_STENCIL 0x4
static void r300EmitClearState(GLcontext * ctx);
static void r600EmitClearState(GLcontext * ctx);
static void r300UserClear(GLcontext *ctx, GLuint mask)
static void r600UserClear(GLcontext *ctx, GLuint mask)
{
radeon_clear_tris(ctx, mask);
}
static void r300ClearBuffer(r300ContextPtr r300, int flags,
static void r600ClearBuffer(r600ContextPtr r600, int flags,
struct radeon_renderbuffer *rrb,
struct radeon_renderbuffer *rrbd)
{
BATCH_LOCALS(&r300->radeon);
GLcontext *ctx = r300->radeon.glCtx;
__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
BATCH_LOCALS(&r600->radeon);
GLcontext *ctx = r600->radeon.glCtx;
__DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
GLuint cbpitch = 0;
r300ContextPtr rmesa = r300;
r600ContextPtr rmesa = r600;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s: buffer %p (%i,%i %ix%i)\n",
@@ -91,25 +91,25 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
if (rrb) {
cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->cpp == 4)
cbpitch |= R300_COLOR_FORMAT_ARGB8888;
cbpitch |= R600_COLOR_FORMAT_ARGB8888;
else
cbpitch |= R300_COLOR_FORMAT_RGB565;
cbpitch |= R600_COLOR_FORMAT_RGB565;
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
cbpitch |= R300_COLOR_TILE_ENABLE;
cbpitch |= R600_COLOR_TILE_ENABLE;
}
}
/* TODO in bufmgr */
cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
end_3d(&rmesa->radeon);
if (flags & CLEARBUFFER_COLOR) {
assert(rrb != 0);
BEGIN_BATCH_NO_AUTOSTATE(6);
OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_BATCH_REGSEQ(R600_RB3D_COLOROFFSET0, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch);
OUT_BATCH_REGVAL(R600_RB3D_COLORPITCH0, cbpitch);
END_BATCH();
}
#if 1
@@ -117,15 +117,15 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
assert(rrbd != 0);
cbpitch = (rrbd->pitch / rrbd->cpp);
if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
cbpitch |= R300_DEPTHMACROTILE_ENABLE;
cbpitch |= R600_DEPTHMACROTILE_ENABLE;
}
if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
cbpitch |= R300_DEPTHMICROTILE_TILED;
cbpitch |= R600_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(6);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_REGSEQ(R600_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch);
OUT_BATCH_REGVAL(R600_ZB_DEPTHPITCH, cbpitch);
END_BATCH();
}
#endif
@@ -148,36 +148,36 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
t2 = 0x0;
if (flags & CLEARBUFFER_DEPTH) {
t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
t1 |= R600_Z_ENABLE | R600_Z_WRITE_ENABLE;
t2 |=
(R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
(R600_ZS_ALWAYS << R600_Z_FUNC_SHIFT);
}
if (flags & CLEARBUFFER_STENCIL) {
t1 |= R300_STENCIL_ENABLE;
t1 |= R600_STENCIL_ENABLE;
t2 |=
(R300_ZS_ALWAYS <<
R300_S_FRONT_FUNC_SHIFT) |
(R300_ZS_REPLACE <<
R300_S_FRONT_SFAIL_OP_SHIFT) |
(R300_ZS_REPLACE <<
R300_S_FRONT_ZPASS_OP_SHIFT) |
(R300_ZS_REPLACE <<
R300_S_FRONT_ZFAIL_OP_SHIFT);
(R600_ZS_ALWAYS <<
R600_S_FRONT_FUNC_SHIFT) |
(R600_ZS_REPLACE <<
R600_S_FRONT_SFAIL_OP_SHIFT) |
(R600_ZS_REPLACE <<
R600_S_FRONT_ZPASS_OP_SHIFT) |
(R600_ZS_REPLACE <<
R600_S_FRONT_ZFAIL_OP_SHIFT);
}
OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
OUT_BATCH_REGSEQ(R600_ZB_CNTL, 3);
OUT_BATCH(t1);
OUT_BATCH(t2);
OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
R300_STENCILWRITEMASK_SHIFT) |
(ctx->Stencil.Clear & R300_STENCILREF_MASK));
OUT_BATCH(((ctx->Stencil.WriteMask[0] & R600_STENCILREF_MASK) <<
R600_STENCILWRITEMASK_SHIFT) |
(ctx->Stencil.Clear & R600_STENCILREF_MASK));
END_BATCH();
}
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(9);
OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
OUT_BATCH(cmdpacket3(r600->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
OUT_BATCH_FLOAT32(dPriv->w / 2.0);
OUT_BATCH_FLOAT32(dPriv->h / 2.0);
OUT_BATCH_FLOAT32(ctx->Depth.Clear);
@@ -189,8 +189,8 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
END_BATCH();
} else {
OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
(1 << R300_PRIM_NUM_VERTICES_SHIFT));
OUT_BATCH(R600_PRIM_TYPE_POINT | R600_PRIM_WALK_RING |
(1 << R600_PRIM_NUM_VERTICES_SHIFT));
OUT_BATCH_FLOAT32(dPriv->w / 2.0);
OUT_BATCH_FLOAT32(dPriv->h / 2.0);
OUT_BATCH_FLOAT32(ctx->Depth.Clear);
@@ -201,28 +201,28 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags,
OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
}
r300EmitCacheFlush(rmesa);
cp_wait(&r300->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
r600EmitCacheFlush(rmesa);
cp_wait(&r600->radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
R300_STATECHANGE(r300, cb);
R300_STATECHANGE(r300, cmk);
R300_STATECHANGE(r300, zs);
R600_STATECHANGE(r600, cb);
R600_STATECHANGE(r600, cmk);
R600_STATECHANGE(r600, zs);
}
static void r300EmitClearState(GLcontext * ctx)
static void r600EmitClearState(GLcontext * ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
r600ContextPtr r600 = R600_CONTEXT(ctx);
BATCH_LOCALS(&r600->radeon);
__DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
int i;
int has_tcl = 1;
int is_r500 = 0;
GLuint vap_cntl;
if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
has_tcl = 0;
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
/* State atom dirty tracking is a little subtle here.
@@ -233,61 +233,61 @@ static void r300EmitClearState(GLcontext * ctx)
* BEGIN_BATCH cannot be a BEGIN_BATCH_NO_AUTOSTATE.
*
* On the other hand, implicit state emission clears the state atom
* dirty bits, so we have to call R300_STATECHANGE later than the
* dirty bits, so we have to call R600_STATECHANGE later than the
* first BEGIN_BATCH.
*
* The final trickiness is that, because we change state, we need
* to ensure that any stored swtcl primitives are flushed properly
* before we start changing state. See the R300_NEWPRIM in r300Clear
* before we start changing state. See the R600_NEWPRIM in r600Clear
* for this.
*/
BEGIN_BATCH(31);
OUT_BATCH_REGSEQ(R300_VAP_PROG_STREAM_CNTL_0, 1);
OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1);
if (!has_tcl)
OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
((R600_LAST_VEC | (2 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
else
OUT_BATCH(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_0_SHIFT) |
((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)));
OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) |
((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT)));
OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
<< R300_SWIZZLE0_SHIFT) |
(((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << R300_WRITE_ENA_SHIFT))
<< R300_SWIZZLE1_SHIFT)));
OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0);
OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0,
((((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) |
(R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) |
(R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) |
(R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) |
((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT))
<< R600_SWIZZLE0_SHIFT) |
(((R600_SWIZZLE_SELECT_X << R600_SWIZZLE_SELECT_X_SHIFT) |
(R600_SWIZZLE_SELECT_Y << R600_SWIZZLE_SELECT_Y_SHIFT) |
(R600_SWIZZLE_SELECT_Z << R600_SWIZZLE_SELECT_Z_SHIFT) |
(R600_SWIZZLE_SELECT_W << R600_SWIZZLE_SELECT_W_SHIFT) |
((R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W) << R600_WRITE_ENA_SHIFT))
<< R600_SWIZZLE1_SHIFT)));
/* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */
OUT_BATCH_REGSEQ(R300_VAP_VTX_STATE_CNTL, 2);
OUT_BATCH((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT));
OUT_BATCH(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0);
/* R600_VAP_INPUT_CNTL_0, R600_VAP_INPUT_CNTL_1 */
OUT_BATCH_REGSEQ(R600_VAP_VTX_STATE_CNTL, 2);
OUT_BATCH((R600_SEL_USER_COLOR_0 << R600_COLOR_0_ASSEMBLY_SHIFT));
OUT_BATCH(R600_INPUT_CNTL_POS | R600_INPUT_CNTL_COLOR | R600_INPUT_CNTL_TC0);
/* comes from fglrx startup of clear */
OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
OUT_BATCH(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA |
R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
R300_VPORT_Z_OFFSET_ENA);
OUT_BATCH_REGSEQ(R600_SE_VTE_CNTL, 2);
OUT_BATCH(R600_VTX_W0_FMT | R600_VPORT_X_SCALE_ENA |
R600_VPORT_X_OFFSET_ENA | R600_VPORT_Y_SCALE_ENA |
R600_VPORT_Y_OFFSET_ENA | R600_VPORT_Z_SCALE_ENA |
R600_VPORT_Z_OFFSET_ENA);
OUT_BATCH(0x8);
OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
OUT_BATCH_REGVAL(R600_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
OUT_BATCH_REGSEQ(R600_VAP_OUTPUT_VTX_FMT_0, 2);
OUT_BATCH(R600_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT |
R600_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT);
OUT_BATCH(0); /* no textures */
OUT_BATCH_REGVAL(R300_TX_ENABLE, 0);
OUT_BATCH_REGVAL(R600_TX_ENABLE, 0);
OUT_BATCH_REGSEQ(R300_SE_VPORT_XSCALE, 6);
OUT_BATCH_REGSEQ(R600_SE_VPORT_XSCALE, 6);
OUT_BATCH_FLOAT32(1.0);
OUT_BATCH_FLOAT32(dPriv->x);
OUT_BATCH_FLOAT32(1.0);
@@ -295,59 +295,59 @@ static void r300EmitClearState(GLcontext * ctx)
OUT_BATCH_FLOAT32(1.0);
OUT_BATCH_FLOAT32(0.0);
OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
OUT_BATCH_REGVAL(R600_FG_ALPHA_FUNC, 0);
OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
OUT_BATCH_REGSEQ(R600_RB3D_CBLEND, 2);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
END_BATCH();
R300_STATECHANGE(r300, vir[0]);
R300_STATECHANGE(r300, fogs);
R300_STATECHANGE(r300, vir[1]);
R300_STATECHANGE(r300, vic);
R300_STATECHANGE(r300, vte);
R300_STATECHANGE(r300, vof);
R300_STATECHANGE(r300, txe);
R300_STATECHANGE(r300, vpt);
R300_STATECHANGE(r300, at);
R300_STATECHANGE(r300, bld);
R300_STATECHANGE(r300, ps);
R600_STATECHANGE(r600, vir[0]);
R600_STATECHANGE(r600, fogs);
R600_STATECHANGE(r600, vir[1]);
R600_STATECHANGE(r600, vic);
R600_STATECHANGE(r600, vte);
R600_STATECHANGE(r600, vof);
R600_STATECHANGE(r600, txe);
R600_STATECHANGE(r600, vpt);
R600_STATECHANGE(r600, at);
R600_STATECHANGE(r600, bld);
R600_STATECHANGE(r600, ps);
if (has_tcl) {
R300_STATECHANGE(r300, vap_clip_cntl);
R600_STATECHANGE(r600, vap_clip_cntl);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE);
OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE);
END_BATCH();
}
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R300_GA_POINT_SIZE,
((dPriv->w * 6) << R300_POINTSIZE_X_SHIFT) |
((dPriv->h * 6) << R300_POINTSIZE_Y_SHIFT));
OUT_BATCH_REGVAL(R600_GA_POINT_SIZE,
((dPriv->w * 6) << R600_POINTSIZE_X_SHIFT) |
((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT));
END_BATCH();
if (!is_r500) {
R300_STATECHANGE(r300, ri);
R300_STATECHANGE(r300, rc);
R300_STATECHANGE(r300, rr);
R600_STATECHANGE(r600, ri);
R600_STATECHANGE(r600, rc);
R600_STATECHANGE(r600, rr);
BEGIN_BATCH(14);
OUT_BATCH_REGSEQ(R300_RS_IP_0, 8);
OUT_BATCH_REGSEQ(R600_RS_IP_0, 8);
for (i = 0; i < 8; ++i)
OUT_BATCH(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3));
OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3));
OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
OUT_BATCH_REGVAL(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE);
END_BATCH();
} else {
R300_STATECHANGE(r300, ri);
R300_STATECHANGE(r300, rc);
R300_STATECHANGE(r300, rr);
R600_STATECHANGE(r600, ri);
R600_STATECHANGE(r600, rc);
R600_STATECHANGE(r600, rr);
BEGIN_BATCH(14);
OUT_BATCH_REGSEQ(R500_RS_IP_0, 8);
@@ -358,8 +358,8 @@ static void r300EmitClearState(GLcontext * ctx)
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
}
OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
OUT_BATCH((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
OUT_BATCH_REGSEQ(R600_RS_COUNT, 2);
OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN);
OUT_BATCH(0x0);
OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
@@ -367,38 +367,38 @@ static void r300EmitClearState(GLcontext * ctx)
}
if (!is_r500) {
R300_STATECHANGE(r300, fp);
R300_STATECHANGE(r300, fpi[0]);
R300_STATECHANGE(r300, fpi[1]);
R300_STATECHANGE(r300, fpi[2]);
R300_STATECHANGE(r300, fpi[3]);
R600_STATECHANGE(r600, fp);
R600_STATECHANGE(r600, fpi[0]);
R600_STATECHANGE(r600, fpi[1]);
R600_STATECHANGE(r600, fpi[2]);
R600_STATECHANGE(r600, fpi[3]);
BEGIN_BATCH(17);
OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
OUT_BATCH_REGSEQ(R600_US_CONFIG, 3);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH(R300_RGBA_OUT);
OUT_BATCH(R600_RGBA_OUT);
OUT_BATCH_REGVAL(R300_US_ALU_RGB_INST_0,
OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0,
FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO)));
OUT_BATCH_REGVAL(R300_US_ALU_RGB_ADDR_0,
OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0,
FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0));
OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_INST_0,
OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0,
FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO)));
OUT_BATCH_REGVAL(R300_US_ALU_ALPHA_ADDR_0,
OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0,
FP_SELA(0, NO, W, FP_TMP(0), 0, 0));
END_BATCH();
} else {
struct radeon_state_atom r500fp;
uint32_t _cmd[10];
R300_STATECHANGE(r300, fp);
R300_STATECHANGE(r300, r500fp);
R600_STATECHANGE(r600, fp);
R600_STATECHANGE(r600, r500fp);
BEGIN_BATCH(7);
OUT_BATCH_REGSEQ(R500_US_CONFIG, 2);
@@ -412,7 +412,7 @@ static void r300EmitClearState(GLcontext * ctx)
r500fp.check = check_r500fp;
r500fp.cmd = _cmd;
r500fp.cmd[0] = cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0);
r500fp.cmd[0] = cmdr500fp(r600->radeon.radeonScreen, 0, 1, 0, 0);
r500fp.cmd[1] = R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
@@ -454,61 +454,61 @@ static void r300EmitClearState(GLcontext * ctx)
}
BEGIN_BATCH(2);
OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0);
END_BATCH();
if (has_tcl) {
vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(12 << R300_VF_MAX_VTX_NUM_SHIFT));
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
(5 << R600_PVS_NUM_CNTLRS_SHIFT) |
(12 << R600_VF_MAX_VTX_NUM_SHIFT));
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
vap_cntl |= R500_TCL_STATE_OPTIMIZATION;
} else {
vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(5 << R300_VF_MAX_VTX_NUM_SHIFT));
vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) |
(5 << R600_PVS_NUM_CNTLRS_SHIFT) |
(5 << R600_VF_MAX_VTX_NUM_SHIFT));
}
if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
(r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515)
vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT);
else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) ||
(r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560) ||
(r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570))
vap_cntl |= (5 << R600_PVS_NUM_FPUS_SHIFT);
else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV410) ||
(r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420))
vap_cntl |= (6 << R600_PVS_NUM_FPUS_SHIFT);
else if ((r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) ||
(r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580))
vap_cntl |= (8 << R600_PVS_NUM_FPUS_SHIFT);
else
vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
vap_cntl |= (4 << R600_PVS_NUM_FPUS_SHIFT);
R300_STATECHANGE(r300, vap_cntl);
R600_STATECHANGE(r600, vap_cntl);
BEGIN_BATCH(2);
OUT_BATCH_REGVAL(R300_VAP_CNTL, vap_cntl);
OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl);
END_BATCH();
if (has_tcl) {
struct radeon_state_atom vpu;
uint32_t _cmd[10];
R300_STATECHANGE(r300, pvs);
R300_STATECHANGE(r300, vpi);
R600_STATECHANGE(r600, pvs);
R600_STATECHANGE(r600, vpi);
BEGIN_BATCH(4);
OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
(0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(1 << R300_PVS_LAST_INST_SHIFT));
OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
(0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
OUT_BATCH_REGSEQ(R600_VAP_PVS_CODE_CNTL_0, 3);
OUT_BATCH((0 << R600_PVS_FIRST_INST_SHIFT) |
(0 << R600_PVS_XYZW_VALID_INST_SHIFT) |
(1 << R600_PVS_LAST_INST_SHIFT));
OUT_BATCH((0 << R600_PVS_CONST_BASE_OFFSET_SHIFT) |
(0 << R600_PVS_MAX_CONST_ADDR_SHIFT));
OUT_BATCH(1 << R600_PVS_LAST_VTX_SRC_INST_SHIFT);
END_BATCH();
vpu.check = check_vpu;
vpu.cmd = _cmd;
vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
vpu.cmd[0] = cmdvpu(r600->radeon.radeonScreen, 0, 2);
vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
0, 0xf, PVS_DST_REG_OUT);
@@ -536,24 +536,24 @@ static void r300EmitClearState(GLcontext * ctx)
PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
vpu.cmd[8] = 0x0;
r300->vap_flush_needed = GL_TRUE;
r600->vap_flush_needed = GL_TRUE;
emit_vpu(ctx, &vpu);
}
}
static void r300KernelClear(GLcontext *ctx, GLuint flags)
static void r600KernelClear(GLcontext *ctx, GLuint flags)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
r600ContextPtr r600 = R600_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
struct radeon_framebuffer *rfb = dPriv->driverPrivate;
struct radeon_renderbuffer *rrb;
struct radeon_renderbuffer *rrbd;
int bits = 0;
/* Make sure it fits there. */
rcommonEnsureCmdBufSpace(&r300->radeon, 421 * 3, __FUNCTION__);
rcommonEnsureCmdBufSpace(&r600->radeon, 421 * 3, __FUNCTION__);
if (flags || bits)
r300EmitClearState(ctx);
r600EmitClearState(ctx);
rrbd = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
if (rrbd && (flags & BUFFER_BIT_DEPTH))
bits |= CLEARBUFFER_DEPTH;
@@ -563,24 +563,24 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags)
if (flags & BUFFER_BIT_COLOR0) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_COLOR0);
r300ClearBuffer(r300, CLEARBUFFER_COLOR, rrb, NULL);
r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL);
bits = 0;
}
if (flags & BUFFER_BIT_FRONT_LEFT) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT);
r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
bits = 0;
}
if (flags & BUFFER_BIT_BACK_LEFT) {
rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_BACK_LEFT);
r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, rrb, rrbd);
r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd);
bits = 0;
}
if (bits)
r300ClearBuffer(r300, bits, NULL, rrbd);
r600ClearBuffer(r600, bits, NULL, rrbd);
COMMIT_BATCH();
}
@@ -588,30 +588,30 @@ static void r300KernelClear(GLcontext *ctx, GLuint flags)
/**
* Buffer clear
*/
static void r300Clear(GLcontext * ctx, GLbitfield mask)
static void r600Clear(GLcontext * ctx, GLbitfield mask)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
r600ContextPtr r600 = R600_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable;
const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
GLbitfield swrast_mask = 0, tri_mask = 0;
int i;
struct gl_framebuffer *fb = ctx->DrawBuffer;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "r300Clear\n");
fprintf(stderr, "r600Clear\n");
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
LOCK_HARDWARE(&r300->radeon);
UNLOCK_HARDWARE(&r300->radeon);
if (!r600->radeon.radeonScreen->driScreen->dri2.enabled) {
LOCK_HARDWARE(&r600->radeon);
UNLOCK_HARDWARE(&r600->radeon);
if (dPriv->numClipRects == 0)
return;
}
/* Flush swtcl vertices if necessary, because we will change hardware
* state during clear. See also the state-related comment in
* r300EmitClearState.
* r600EmitClearState.
*/
R300_NEWPRIM(r300);
R600_NEWPRIM(r600);
if (colorMask == ~0)
tri_mask |= (mask & BUFFER_BITS_COLOR);
@@ -645,10 +645,10 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
swrast_mask = mask & ~tri_mask;
if (tri_mask) {
if (r300->radeon.radeonScreen->kernel_mm)
r300UserClear(ctx, tri_mask);
if (r600->radeon.radeonScreen->kernel_mm)
r600UserClear(ctx, tri_mask);
else
r300KernelClear(ctx, tri_mask);
r600KernelClear(ctx, tri_mask);
}
if (swrast_mask) {
if (RADEON_DEBUG & DEBUG_FALLBACKS)
@@ -659,9 +659,9 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask)
}
void r300InitIoctlFuncs(struct dd_function_table *functions)
void r600InitIoctlFuncs(struct dd_function_table *functions)
{
functions->Clear = r300Clear;
functions->Clear = r600Clear;
functions->Finish = radeonFinish;
functions->Flush = radeonFlush;
}
src/mesa/drivers/dri/r600/r600_ioctl.h
+1 -1
View File
@@ -39,6 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r600_context.h"
#include "radeon_drm.h"
extern void r300InitIoctlFuncs(struct dd_function_table *functions);
extern void r600InitIoctlFuncs(struct dd_function_table *functions);
#endif /* __R600_IOCTL_H__ */
src/mesa/drivers/dri/r600/r600_reg.h
+1369 -1369
View File
File diff suppressed because it is too large Load Diff
src/mesa/drivers/dri/r600/r600_render.c
+77 -77
View File
@@ -28,7 +28,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/**
* \file
*
* \brief R300 Render (Vertex Buffer Implementation)
* \brief R600 Render (Vertex Buffer Implementation)
*
* The immediate implementation has been removed from CVS in favor of the vertex
* buffer implementation.
@@ -76,40 +76,40 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
extern int future_hw_tcl_on;
/**
* \brief Convert a OpenGL primitive type into a R300 primitive type.
* \brief Convert a OpenGL primitive type into a R600 primitive type.
*/
int r300PrimitiveType(r300ContextPtr rmesa, int prim)
int r600PrimitiveType(r600ContextPtr rmesa, int prim)
{
switch (prim & PRIM_MODE_MASK) {
case GL_POINTS:
return R300_VAP_VF_CNTL__PRIM_POINTS;
return R600_VAP_VF_CNTL__PRIM_POINTS;
break;
case GL_LINES:
return R300_VAP_VF_CNTL__PRIM_LINES;
return R600_VAP_VF_CNTL__PRIM_LINES;
break;
case GL_LINE_STRIP:
return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
return R600_VAP_VF_CNTL__PRIM_LINE_STRIP;
break;
case GL_LINE_LOOP:
return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
return R600_VAP_VF_CNTL__PRIM_LINE_LOOP;
break;
case GL_TRIANGLES:
return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
return R600_VAP_VF_CNTL__PRIM_TRIANGLES;
break;
case GL_TRIANGLE_STRIP:
return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
return R600_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
break;
case GL_TRIANGLE_FAN:
return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
return R600_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
break;
case GL_QUADS:
return R300_VAP_VF_CNTL__PRIM_QUADS;
return R600_VAP_VF_CNTL__PRIM_QUADS;
break;
case GL_QUAD_STRIP:
return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
return R600_VAP_VF_CNTL__PRIM_QUAD_STRIP;
break;
case GL_POLYGON:
return R300_VAP_VF_CNTL__PRIM_POLYGON;
return R600_VAP_VF_CNTL__PRIM_POLYGON;
break;
default:
assert(0);
@@ -118,7 +118,7 @@ int r300PrimitiveType(r300ContextPtr rmesa, int prim)
}
}
int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim)
int r600NumVerts(r600ContextPtr rmesa, int num_verts, int prim)
{
int verts_off = 0;
@@ -170,9 +170,9 @@ int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim)
return num_verts - verts_off;
}
static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts)
static void r600EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
void *out;
radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo,
@@ -183,31 +183,31 @@ static void r300EmitElts(GLcontext * ctx, void *elts, unsigned long n_elts)
radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
}
static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
static void r600FireEB(r600ContextPtr rmesa, int vertex_count, int type)
{
BATCH_LOCALS(&rmesa->radeon);
if (vertex_count > 0) {
BEGIN_BATCH(10);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_INDX_2, 0);
OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_INDICES |
((vertex_count + 0) << 16) |
type |
R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
R600_VAP_VF_CNTL__INDEX_SIZE_32bit);
if (!rmesa->radeon.radeonScreen->kernel_mm) {
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
(R300_VAP_PORT_IDX0 >> 2));
OUT_BATCH_PACKET3(R600_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R600_INDX_BUFFER_ONE_REG_WR | (0 << R600_INDX_BUFFER_SKIP_SHIFT) |
(R600_VAP_PORT_IDX0 >> 2));
OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
rmesa->radeon.tcl.elt_dma_bo,
rmesa->radeon.tcl.elt_dma_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(vertex_count);
} else {
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
(R300_VAP_PORT_IDX0 >> 2));
OUT_BATCH_PACKET3(R600_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R600_INDX_BUFFER_ONE_REG_WR | (0 << R600_INDX_BUFFER_SKIP_SHIFT) |
(R600_VAP_PORT_IDX0 >> 2));
OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
OUT_BATCH(vertex_count);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
@@ -218,7 +218,7 @@ static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type)
}
}
static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
static void r600EmitAOS(r600ContextPtr rmesa, GLuint nr, GLuint offset)
{
BATCH_LOCALS(&rmesa->radeon);
uint32_t voffset;
@@ -232,7 +232,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH(sz+2+(nr * 2));
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
@@ -272,7 +272,7 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
} else {
BEGIN_BATCH(sz+2+(nr * 2));
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
@@ -323,25 +323,25 @@ static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
}
static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type)
static void r600FireAOS(r600ContextPtr rmesa, int vertex_count, int type)
{
BATCH_LOCALS(&rmesa->radeon);
BEGIN_BATCH(3);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
END_BATCH();
}
static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx,
static void r600RunRenderPrimitive(r600ContextPtr rmesa, GLcontext * ctx,
int start, int end, int prim)
{
int type, num_verts;
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
type = r300PrimitiveType(rmesa, prim);
num_verts = r300NumVerts(rmesa, end - start, prim);
type = r600PrimitiveType(rmesa, prim);
num_verts = r600NumVerts(rmesa, end - start, prim);
if (type < 0 || num_verts <= 0)
return;
@@ -369,20 +369,20 @@ static void r300RunRenderPrimitive(r300ContextPtr rmesa, GLcontext * ctx,
* allocating the index array might actually evict the vertex
* arrays. *sigh*
*/
r300EmitElts(ctx, vb->Elts, num_verts);
r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
r300FireEB(rmesa, num_verts, type);
r600EmitElts(ctx, vb->Elts, num_verts);
r600EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
r600FireEB(rmesa, num_verts, type);
} else {
r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
r300FireAOS(rmesa, num_verts, type);
r600EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start);
r600FireAOS(rmesa, num_verts, type);
}
COMMIT_BATCH();
}
static GLboolean r300RunRender(GLcontext * ctx,
static GLboolean r600RunRender(GLcontext * ctx,
struct tnl_pipeline_stage *stage)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
int i;
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *vb = &tnl->vb;
@@ -390,23 +390,23 @@ static GLboolean r300RunRender(GLcontext * ctx,
if (RADEON_DEBUG & DEBUG_PRIMS)
fprintf(stderr, "%s\n", __FUNCTION__);
r300UpdateShaders(rmesa);
if (r300EmitArrays(ctx))
r600UpdateShaders(rmesa);
if (r600EmitArrays(ctx))
return GL_TRUE;
r300UpdateShaderStates(rmesa);
r600UpdateShaderStates(rmesa);
r300EmitCacheFlush(rmesa);
r600EmitCacheFlush(rmesa);
radeonEmitState(&rmesa->radeon);
for (i = 0; i < vb->PrimitiveCount; i++) {
GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
GLuint start = vb->Primitive[i].start;
GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
r300RunRenderPrimitive(rmesa, ctx, start, end, prim);
r600RunRenderPrimitive(rmesa, ctx, start, end, prim);
}
r300EmitCacheFlush(rmesa);
r600EmitCacheFlush(rmesa);
radeonReleaseArrays(ctx, ~0);
@@ -419,33 +419,33 @@ static GLboolean r300RunRender(GLcontext * ctx,
if (1 || RADEON_DEBUG & DEBUG_FALLBACKS) \
WARN_ONCE("Software fallback:%s\n", \
#expr); \
return R300_FALLBACK_RAST; \
return R600_FALLBACK_RAST; \
} \
} while(0)
static int r300Fallback(GLcontext * ctx)
static int r600Fallback(GLcontext * ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
r600ContextPtr r600 = R600_CONTEXT(ctx);
const unsigned back = ctx->Stencil._BackFace;
FALLBACK_IF(r300->radeon.Fallback);
FALLBACK_IF(r600->radeon.Fallback);
/* Do we need to use new-style shaders?
* Also is there a better way to do this? */
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
struct r500_fragment_program *fp = (struct r500_fragment_program *)
(char *)ctx->FragmentProgram._Current;
if (fp) {
if (!fp->translated) {
r500TranslateFragmentShader(r300, fp);
r500TranslateFragmentShader(r600, fp);
FALLBACK_IF(!fp->translated);
}
}
} else {
struct r300_fragment_program *fp = (struct r300_fragment_program *)
struct r600_fragment_program *fp = (struct r600_fragment_program *)
(char *)ctx->FragmentProgram._Current;
if (fp) {
if (!fp->translated) {
r300TranslateFragmentShader(r300, fp);
r600TranslateFragmentShader(r600, fp);
FALLBACK_IF(!fp->translated);
}
}
@@ -465,7 +465,7 @@ static int r300Fallback(GLcontext * ctx)
if (ctx->Extensions.NV_point_sprite || ctx->Extensions.ARB_point_sprite)
FALLBACK_IF(ctx->Point.PointSprite);
if (!r300->disable_lowimpact_fallback) {
if (!r600->disable_lowimpact_fallback) {
FALLBACK_IF(ctx->Polygon.StippleFlag);
FALLBACK_IF(ctx->Multisample._Enabled);
FALLBACK_IF(ctx->Line.StippleFlag);
@@ -473,34 +473,34 @@ static int r300Fallback(GLcontext * ctx)
FALLBACK_IF(ctx->Point.SmoothFlag);
}
return R300_FALLBACK_NONE;
return R600_FALLBACK_NONE;
}
static GLboolean r300RunNonTCLRender(GLcontext * ctx,
static GLboolean r600RunNonTCLRender(GLcontext * ctx,
struct tnl_pipeline_stage *stage)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
if (RADEON_DEBUG & DEBUG_PRIMS)
fprintf(stderr, "%s\n", __FUNCTION__);
if (r300Fallback(ctx) >= R300_FALLBACK_RAST)
if (r600Fallback(ctx) >= R600_FALLBACK_RAST)
return GL_TRUE;
if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
return GL_TRUE;
if (!r300ValidateBuffers(ctx))
if (!r600ValidateBuffers(ctx))
return GL_TRUE;
return r300RunRender(ctx, stage);
return r600RunRender(ctx, stage);
}
static GLboolean r300RunTCLRender(GLcontext * ctx,
static GLboolean r600RunTCLRender(GLcontext * ctx,
struct tnl_pipeline_stage *stage)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
struct r300_vertex_program *vp;
r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct r600_vertex_program *vp;
hw_tcl_on = future_hw_tcl_on;
@@ -510,39 +510,39 @@ static GLboolean r300RunTCLRender(GLcontext * ctx,
if (hw_tcl_on == GL_FALSE)
return GL_TRUE;
if (r300Fallback(ctx) >= R300_FALLBACK_TCL) {
if (r600Fallback(ctx) >= R600_FALLBACK_TCL) {
hw_tcl_on = GL_FALSE;
return GL_TRUE;
}
if (!r300ValidateBuffers(ctx))
if (!r600ValidateBuffers(ctx))
return GL_TRUE;
r300UpdateShaders(rmesa);
r600UpdateShaders(rmesa);
vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
vp = (struct r600_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
if (vp->native == GL_FALSE) {
hw_tcl_on = GL_FALSE;
return GL_TRUE;
}
return r300RunRender(ctx, stage);
return r600RunRender(ctx, stage);
}
const struct tnl_pipeline_stage _r300_render_stage = {
"r300 Hardware Rasterization",
const struct tnl_pipeline_stage _r600_render_stage = {
"r600 Hardware Rasterization",
NULL,
NULL,
NULL,
NULL,
r300RunNonTCLRender
r600RunNonTCLRender
};
const struct tnl_pipeline_stage _r300_tcl_stage = {
"r300 Hardware Transform, Clipping and Lighting",
const struct tnl_pipeline_stage _r600_tcl_stage = {
"r600 Hardware Transform, Clipping and Lighting",
NULL,
NULL,
NULL,
NULL,
r300RunTCLRender
r600RunTCLRender
};
src/mesa/drivers/dri/r600/r600_shader.c
+22 -22
View File
@@ -6,18 +6,18 @@
#include "r600_context.h"
#include "r600_fragprog.h"
static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target,
static struct gl_program *r600NewProgram(GLcontext * ctx, GLenum target,
GLuint id)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
struct r300_vertex_program_cont *vp;
struct r300_fragment_program *r300_fp;
r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct r600_vertex_program_cont *vp;
struct r600_fragment_program *r600_fp;
struct r500_fragment_program *r500_fp;
switch (target) {
case GL_VERTEX_STATE_PROGRAM_NV:
case GL_VERTEX_PROGRAM_ARB:
vp = CALLOC_STRUCT(r300_vertex_program_cont);
vp = CALLOC_STRUCT(r600_vertex_program_cont);
return _mesa_init_vertex_program(ctx, &vp->mesa_program,
target, id);
case GL_FRAGMENT_PROGRAM_ARB:
@@ -27,8 +27,8 @@ static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target,
return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program,
target, id);
} else {
r300_fp = CALLOC_STRUCT(r300_fragment_program);
return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program,
r600_fp = CALLOC_STRUCT(r600_fragment_program);
return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
}
@@ -38,28 +38,28 @@ static struct gl_program *r300NewProgram(GLcontext * ctx, GLenum target,
return _mesa_init_fragment_program(ctx, &r500_fp->mesa_program,
target, id);
} else {
r300_fp = CALLOC_STRUCT(r300_fragment_program);
return _mesa_init_fragment_program(ctx, &r300_fp->mesa_program,
r600_fp = CALLOC_STRUCT(r600_fragment_program);
return _mesa_init_fragment_program(ctx, &r600_fp->mesa_program,
target, id);
}
default:
_mesa_problem(ctx, "Bad target in r300NewProgram");
_mesa_problem(ctx, "Bad target in r600NewProgram");
}
return NULL;
}
static void r300DeleteProgram(GLcontext * ctx, struct gl_program *prog)
static void r600DeleteProgram(GLcontext * ctx, struct gl_program *prog)
{
_mesa_delete_program(ctx, prog);
}
static void
r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
r600ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
struct r300_vertex_program_cont *vp = (void *)prog;
struct r300_fragment_program *r300_fp = (struct r300_fragment_program *)prog;
r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct r600_vertex_program_cont *vp = (void *)prog;
struct r600_fragment_program *r600_fp = (struct r600_fragment_program *)prog;
struct r500_fragment_program *r500_fp = (struct r500_fragment_program *)prog;
switch (target) {
@@ -70,7 +70,7 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
r500_fp->translated = GL_FALSE;
else
r300_fp->translated = GL_FALSE;
r600_fp->translated = GL_FALSE;
break;
}
@@ -79,15 +79,15 @@ r300ProgramStringNotify(GLcontext * ctx, GLenum target, struct gl_program *prog)
}
static GLboolean
r300IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog)
r600IsProgramNative(GLcontext * ctx, GLenum target, struct gl_program *prog)
{
return GL_TRUE;
}
void r300InitShaderFuncs(struct dd_function_table *functions)
void r600InitShaderFuncs(struct dd_function_table *functions)
{
functions->NewProgram = r300NewProgram;
functions->DeleteProgram = r300DeleteProgram;
functions->ProgramStringNotify = r300ProgramStringNotify;
functions->IsProgramNative = r300IsProgramNative;
functions->NewProgram = r600NewProgram;
functions->DeleteProgram = r600DeleteProgram;
functions->ProgramStringNotify = r600ProgramStringNotify;
functions->IsProgramNative = r600IsProgramNative;
}
src/mesa/drivers/dri/r600/r600_state.c
+775 -775
View File
File diff suppressed because it is too large Load Diff
src/mesa/drivers/dri/r600/r600_state.h
+15 -15
View File
@@ -37,29 +37,29 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "r600_context.h"
#define R300_NEWPRIM( rmesa ) \
#define R600_NEWPRIM( rmesa ) \
do { \
if ( rmesa->radeon.dma.flush ) \
rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
} while (0)
#define R300_STATECHANGE(r300, atom) \
#define R600_STATECHANGE(r600, atom) \
do { \
R300_NEWPRIM(r300); \
r300->hw.atom.dirty = GL_TRUE; \
r300->radeon.hw.is_dirty = GL_TRUE; \
R600_NEWPRIM(r600); \
r600->hw.atom.dirty = GL_TRUE; \
r600->radeon.hw.is_dirty = GL_TRUE; \
} while(0)
// r300_state.c
// r600_state.c
extern int future_hw_tcl_on;
void _tnl_UpdateFixedFunctionProgram (GLcontext * ctx);
void r300UpdateViewportOffset (GLcontext * ctx);
void r300UpdateDrawBuffer (GLcontext * ctx);
void r300UpdateStateParameters (GLcontext * ctx, GLuint new_state);
void r300UpdateShaders (r300ContextPtr rmesa);
void r300UpdateShaderStates (r300ContextPtr rmesa);
void r300InitState (r300ContextPtr r300);
void r300UpdateClipPlanes (GLcontext * ctx);
void r300InitStateFuncs (struct dd_function_table *functions);
void r600UpdateViewportOffset (GLcontext * ctx);
void r600UpdateDrawBuffer (GLcontext * ctx);
void r600UpdateStateParameters (GLcontext * ctx, GLuint new_state);
void r600UpdateShaders (r600ContextPtr rmesa);
void r600UpdateShaderStates (r600ContextPtr rmesa);
void r600InitState (r600ContextPtr r600);
void r600UpdateClipPlanes (GLcontext * ctx);
void r600InitStateFuncs (struct dd_function_table *functions);
#endif /* __R300_STATE_H__ */
#endif /* __R600_STATE_H__ */
src/mesa/drivers/dri/r600/r600_swtcl.c
+107 -107
View File
@@ -63,9 +63,9 @@ do { \
++num_attrs; \
} while (0)
static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten)
static void r600SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsWritten)
{
r300ContextPtr rmesa = R300_CONTEXT( ctx );
r600ContextPtr rmesa = R600_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
struct vertex_attribute *attrs = rmesa->swtcl.vert_attrs;
@@ -74,27 +74,27 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW
uint32_t *vir0 = &rmesa->hw.vir[0].cmd[1];
uint32_t *vir1 = &rmesa->hw.vir[1].cmd[1];
for (i = 0; i < R300_VIR_CMDSIZE-1; ++i)
for (i = 0; i < R600_VIR_CMDSIZE-1; ++i)
vir0[i] = vir1[i] = 0;
for (i = 0, j = 0; i < rmesa->radeon.swtcl.vertex_attr_count; ++i) {
int tmp, data_format;
switch (attrs[i].format) {
case EMIT_1F:
data_format = R300_DATA_TYPE_FLOAT_1;
data_format = R600_DATA_TYPE_FLOAT_1;
break;
case EMIT_2F:
data_format = R300_DATA_TYPE_FLOAT_2;
data_format = R600_DATA_TYPE_FLOAT_2;
break;
case EMIT_3F:
data_format = R300_DATA_TYPE_FLOAT_3;
data_format = R600_DATA_TYPE_FLOAT_3;
break;
case EMIT_4F:
data_format = R300_DATA_TYPE_FLOAT_4;
data_format = R600_DATA_TYPE_FLOAT_4;
break;
case EMIT_4UB_4F_RGBA:
case EMIT_4UB_4F_ABGR:
data_format = R300_DATA_TYPE_BYTE | R300_NORMALIZE;
data_format = R600_DATA_TYPE_BYTE | R600_NORMALIZE;
break;
default:
fprintf(stderr, "%s: Invalid data format type", __FUNCTION__);
@@ -102,29 +102,29 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW
break;
}
tmp = data_format | (attrs[i].dst_loc << R300_DST_VEC_LOC_SHIFT);
tmp = data_format | (attrs[i].dst_loc << R600_DST_VEC_LOC_SHIFT);
if (i % 2 == 0) {
vir0[j] = tmp << R300_DATA_TYPE_0_SHIFT;
vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT);
vir0[j] = tmp << R600_DATA_TYPE_0_SHIFT;
vir1[j] = attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT);
} else {
vir0[j] |= tmp << R300_DATA_TYPE_1_SHIFT;
vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT;
vir0[j] |= tmp << R600_DATA_TYPE_1_SHIFT;
vir1[j] |= (attrs[i].swizzle | (attrs[i].write_mask << R600_WRITE_ENA_SHIFT)) << R600_SWIZZLE1_SHIFT;
++j;
}
}
reg_count = (rmesa->radeon.swtcl.vertex_attr_count + 1) >> 1;
if (rmesa->radeon.swtcl.vertex_attr_count % 2 != 0) {
vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_0_SHIFT;
vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_0_SHIFT;
} else {
vir0[reg_count-1] |= R300_LAST_VEC << R300_DATA_TYPE_1_SHIFT;
vir0[reg_count-1] |= R600_LAST_VEC << R600_DATA_TYPE_1_SHIFT;
}
R300_STATECHANGE(rmesa, vir[0]);
R300_STATECHANGE(rmesa, vir[1]);
R300_STATECHANGE(rmesa, vof);
R300_STATECHANGE(rmesa, vte);
R300_STATECHANGE(rmesa, vic);
R600_STATECHANGE(rmesa, vir[0]);
R600_STATECHANGE(rmesa, vir[1]);
R600_STATECHANGE(rmesa, vof);
R600_STATECHANGE(rmesa, vte);
R600_STATECHANGE(rmesa, vic);
if (rmesa->radeon.radeonScreen->kernel_mm) {
rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF;
@@ -136,22 +136,22 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW
((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count = reg_count;
}
rmesa->hw.vic.cmd[R300_VIC_CNTL_0] = r300VAPInputCntl0(ctx, InputsRead);
rmesa->hw.vic.cmd[R300_VIC_CNTL_1] = r300VAPInputCntl1(ctx, InputsRead);
rmesa->hw.vof.cmd[R300_VOF_CNTL_0] = r300VAPOutputCntl0(ctx, OutputsWritten);
rmesa->hw.vof.cmd[R300_VOF_CNTL_1] = r300VAPOutputCntl1(ctx, OutputsWritten);
rmesa->hw.vic.cmd[R600_VIC_CNTL_0] = r600VAPInputCntl0(ctx, InputsRead);
rmesa->hw.vic.cmd[R600_VIC_CNTL_1] = r600VAPInputCntl1(ctx, InputsRead);
rmesa->hw.vof.cmd[R600_VOF_CNTL_0] = r600VAPOutputCntl0(ctx, OutputsWritten);
rmesa->hw.vof.cmd[R600_VOF_CNTL_1] = r600VAPOutputCntl1(ctx, OutputsWritten);
vte = rmesa->hw.vte.cmd[1];
vte &= ~(R300_VTX_XY_FMT | R300_VTX_Z_FMT | R300_VTX_W0_FMT);
vte &= ~(R600_VTX_XY_FMT | R600_VTX_Z_FMT | R600_VTX_W0_FMT);
/* Important:
*/
if ( VB->NdcPtr != NULL ) {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
vte |= R300_VTX_XY_FMT | R300_VTX_Z_FMT;
vte |= R600_VTX_XY_FMT | R600_VTX_Z_FMT;
}
else {
VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
vte |= R300_VTX_W0_FMT;
vte |= R600_VTX_W0_FMT;
}
assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
@@ -161,9 +161,9 @@ static void r300SwtclVAPSetup(GLcontext *ctx, GLuint InputsRead, GLuint OutputsW
}
static void r300SetVertexFormat( GLcontext *ctx )
static void r600SetVertexFormat( GLcontext *ctx )
{
r300ContextPtr rmesa = R300_CONTEXT( ctx );
r600ContextPtr rmesa = R600_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
int fog_id = -1;
@@ -306,8 +306,8 @@ static void r300SetVertexFormat( GLcontext *ctx )
ADD_ATTR(VERT_ATTRIB_TEX0 + first_free_tex, EMIT_4F, SWTCL_OVM_TEX(first_free_tex), SWIZZLE_XYZW, MASK_XYZW);
}
R300_NEWPRIM(rmesa);
r300SwtclVAPSetup(ctx, InputsRead, OutputsWritten);
R600_NEWPRIM(rmesa);
r600SwtclVAPSetup(ctx, InputsRead, OutputsWritten);
rmesa->radeon.swtcl.vertex_size =
_tnl_install_attrs( ctx,
@@ -334,8 +334,8 @@ static GLuint reduced_prim[] = {
GL_TRIANGLES,
};
static void r300RasterPrimitive( GLcontext *ctx, GLuint prim );
static void r300RenderPrimitive( GLcontext *ctx, GLenum prim );
static void r600RasterPrimitive( GLcontext *ctx, GLuint prim );
static void r600RenderPrimitive( GLcontext *ctx, GLenum prim );
/***********************************************************************
* Emit primitives as inline vertices *
@@ -356,16 +356,16 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim );
#undef LOCAL_VARS
#undef ALLOC_VERTS
#define CTX_ARG r300ContextPtr rmesa
#define CTX_ARG r600ContextPtr rmesa
#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
#define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 )
#define LOCAL_VARS \
r300ContextPtr rmesa = R300_CONTEXT(ctx); \
const char *r300verts = (char *)rmesa->radeon.swtcl.verts;
#define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int)))
#define VERTEX r300Vertex
r600ContextPtr rmesa = R600_CONTEXT(ctx); \
const char *r600verts = (char *)rmesa->radeon.swtcl.verts;
#define VERT(x) (r600Vertex *)(r600verts + ((x) * vertsize * sizeof(int)))
#define VERTEX r600Vertex
#undef TAG
#define TAG(x) r300_##x
#define TAG(x) r600_##x
#include "tnl_dd/t_dd_triemit.h"
@@ -374,29 +374,29 @@ static void r300RenderPrimitive( GLcontext *ctx, GLenum prim );
* Macros for t_dd_tritmp.h to draw basic primitives *
***********************************************************************/
#define QUAD( a, b, c, d ) r300_quad( rmesa, a, b, c, d )
#define TRI( a, b, c ) r300_triangle( rmesa, a, b, c )
#define LINE( a, b ) r300_line( rmesa, a, b )
#define POINT( a ) r300_point( rmesa, a )
#define QUAD( a, b, c, d ) r600_quad( rmesa, a, b, c, d )
#define TRI( a, b, c ) r600_triangle( rmesa, a, b, c )
#define LINE( a, b ) r600_line( rmesa, a, b )
#define POINT( a ) r600_point( rmesa, a )
/***********************************************************************
* Build render functions from dd templates *
***********************************************************************/
#define R300_TWOSIDE_BIT 0x01
#define R300_UNFILLED_BIT 0x02
#define R300_MAX_TRIFUNC 0x04
#define R600_TWOSIDE_BIT 0x01
#define R600_UNFILLED_BIT 0x02
#define R600_MAX_TRIFUNC 0x04
static struct {
tnl_points_func points;
tnl_line_func line;
tnl_triangle_func triangle;
tnl_quad_func quad;
} rast_tab[R300_MAX_TRIFUNC];
} rast_tab[R600_MAX_TRIFUNC];
#define DO_FALLBACK 0
#define DO_UNFILLED (IND & R300_UNFILLED_BIT)
#define DO_TWOSIDE (IND & R300_TWOSIDE_BIT)
#define DO_UNFILLED (IND & R600_UNFILLED_BIT)
#define DO_TWOSIDE (IND & R600_TWOSIDE_BIT)
#define DO_FLAT 0
#define DO_OFFSET 0
#define DO_TRI 1
@@ -422,7 +422,7 @@ static struct {
#define VERT_SET_RGBA( v, c ) \
do { \
r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \
r600_color_t *color = (r600_color_t *)&((v)->ui[coloroffset]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
@@ -459,7 +459,7 @@ do { \
#undef INIT
#define LOCAL_VARS(n) \
r300ContextPtr rmesa = R300_CONTEXT(ctx); \
r600ContextPtr rmesa = R600_CONTEXT(ctx); \
GLuint color[n] = { 0, }, spec[n] = { 0, }; \
GLuint coloroffset = rmesa->swtcl.coloroffset; \
GLuint specoffset = rmesa->swtcl.specoffset; \
@@ -469,7 +469,7 @@ do { \
* Helpers for rendering unfilled primitives *
***********************************************************************/
#define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] )
#define RASTERIZE(x) r600RasterPrimitive( ctx, reduced_prim[x] )
#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
#undef TAG
#define TAG(x) x
@@ -486,15 +486,15 @@ do { \
#define TAG(x) x
#include "tnl_dd/t_dd_tritmp.h"
#define IND (R300_TWOSIDE_BIT)
#define IND (R600_TWOSIDE_BIT)
#define TAG(x) x##_twoside
#include "tnl_dd/t_dd_tritmp.h"
#define IND (R300_UNFILLED_BIT)
#define IND (R600_UNFILLED_BIT)
#define TAG(x) x##_unfilled
#include "tnl_dd/t_dd_tritmp.h"
#define IND (R300_TWOSIDE_BIT|R300_UNFILLED_BIT)
#define IND (R600_TWOSIDE_BIT|R600_UNFILLED_BIT)
#define TAG(x) x##_twoside_unfilled
#include "tnl_dd/t_dd_tritmp.h"
@@ -514,21 +514,21 @@ static void init_rast_tab( void )
#define RENDER_POINTS( start, count ) \
for ( ; start < count ; start++) \
r300_point( rmesa, VERT(start) )
r600_point( rmesa, VERT(start) )
#define RENDER_LINE( v0, v1 ) \
r300_line( rmesa, VERT(v0), VERT(v1) )
r600_line( rmesa, VERT(v0), VERT(v1) )
#define RENDER_TRI( v0, v1, v2 ) \
r300_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
r600_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
#define RENDER_QUAD( v0, v1, v2, v3 ) \
r300_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
r600_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
#define INIT(x) do { \
r300RenderPrimitive( ctx, x ); \
r600RenderPrimitive( ctx, x ); \
} while (0)
#undef LOCAL_VARS
#define LOCAL_VARS \
r300ContextPtr rmesa = R300_CONTEXT(ctx); \
r600ContextPtr rmesa = R600_CONTEXT(ctx); \
const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \
const char *r600verts = (char *)rmesa->radeon.swtcl.verts; \
const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
const GLboolean stipple = ctx->Line.StippleFlag; \
(void) elt; (void) stipple;
@@ -536,11 +536,11 @@ static void init_rast_tab( void )
#define RESET_OCCLUSION
#define PRESERVE_VB_DEFS
#define ELT(x) (x)
#define TAG(x) r300_##x##_verts
#define TAG(x) r600_##x##_verts
#include "tnl/t_vb_rendertmp.h"
#undef ELT
#undef TAG
#define TAG(x) r300_##x##_elts
#define TAG(x) r600_##x##_elts
#define ELT(x) elt[x]
#include "tnl/t_vb_rendertmp.h"
@@ -550,15 +550,15 @@ static void init_rast_tab( void )
/**********************************************************************/
/* Choose render functions */
/**********************************************************************/
static void r300ChooseRenderState( GLcontext *ctx )
static void r600ChooseRenderState( GLcontext *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
GLuint index = 0;
GLuint flags = ctx->_TriangleCaps;
if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R300_TWOSIDE_BIT;
if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT;
if (flags & DD_TRI_LIGHT_TWOSIDE) index |= R600_TWOSIDE_BIT;
if (flags & DD_TRI_UNFILLED) index |= R600_UNFILLED_BIT;
if (index != rmesa->radeon.swtcl.RenderIndex) {
tnl->Driver.Render.Points = rast_tab[index].points;
@@ -568,9 +568,9 @@ static void r300ChooseRenderState( GLcontext *ctx )
tnl->Driver.Render.Quad = rast_tab[index].quad;
if (index == 0) {
tnl->Driver.Render.PrimTabVerts = r300_render_tab_verts;
tnl->Driver.Render.PrimTabElts = r300_render_tab_elts;
tnl->Driver.Render.ClippedPolygon = r300_fast_clipped_poly;
tnl->Driver.Render.PrimTabVerts = r600_render_tab_verts;
tnl->Driver.Render.PrimTabElts = r600_render_tab_elts;
tnl->Driver.Render.ClippedPolygon = r600_fast_clipped_poly;
} else {
tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
@@ -582,19 +582,19 @@ static void r300ChooseRenderState( GLcontext *ctx )
}
static void r300RenderStart(GLcontext *ctx)
static void r600RenderStart(GLcontext *ctx)
{
r300ContextPtr rmesa = R300_CONTEXT( ctx );
r600ContextPtr rmesa = R600_CONTEXT( ctx );
r300ChooseRenderState(ctx);
r300SetVertexFormat(ctx);
r600ChooseRenderState(ctx);
r600SetVertexFormat(ctx);
r300ValidateBuffers(ctx);
r600ValidateBuffers(ctx);
r300UpdateShaders(rmesa);
r300UpdateShaderStates(rmesa);
r600UpdateShaders(rmesa);
r600UpdateShaderStates(rmesa);
r300EmitCacheFlush(rmesa);
r600EmitCacheFlush(rmesa);
/* investigate if we can put back flush optimisation if needed */
if (rmesa->radeon.dma.flush != NULL) {
@@ -602,40 +602,40 @@ static void r300RenderStart(GLcontext *ctx)
}
}
static void r300RenderFinish(GLcontext *ctx)
static void r600RenderFinish(GLcontext *ctx)
{
}
static void r300RasterPrimitive( GLcontext *ctx, GLuint hwprim )
static void r600RasterPrimitive( GLcontext *ctx, GLuint hwprim )
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
R300_NEWPRIM( rmesa );
R600_NEWPRIM( rmesa );
rmesa->radeon.swtcl.hw_primitive = hwprim;
}
}
static void r300RenderPrimitive(GLcontext *ctx, GLenum prim)
static void r600RenderPrimitive(GLcontext *ctx, GLenum prim)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
rmesa->radeon.swtcl.render_primitive = prim;
if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED))
return;
r300RasterPrimitive( ctx, reduced_prim[prim] );
r600RasterPrimitive( ctx, reduced_prim[prim] );
}
static void r300ResetLineStipple(GLcontext *ctx)
static void r600ResetLineStipple(GLcontext *ctx)
{
}
void r300InitSwtcl(GLcontext *ctx)
void r600InitSwtcl(GLcontext *ctx)
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
static int firsttime = 1;
if (firsttime) {
@@ -643,10 +643,10 @@ void r300InitSwtcl(GLcontext *ctx)
firsttime = 0;
}
tnl->Driver.Render.Start = r300RenderStart;
tnl->Driver.Render.Finish = r300RenderFinish;
tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
tnl->Driver.Render.Start = r600RenderStart;
tnl->Driver.Render.Finish = r600RenderFinish;
tnl->Driver.Render.PrimitiveNotify = r600RenderPrimitive;
tnl->Driver.Render.ResetLineStipple = r600ResetLineStipple;
tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
@@ -664,14 +664,14 @@ void r300InitSwtcl(GLcontext *ctx)
_tnl_invalidate_vertices( ctx, ~0 );
_tnl_need_projected_coords( ctx, GL_FALSE );
r300ChooseRenderState(ctx);
r600ChooseRenderState(ctx);
}
void r300DestroySwtcl(GLcontext *ctx)
void r600DestroySwtcl(GLcontext *ctx)
{
}
static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
{
BATCH_LOCALS(&rmesa->radeon);
@@ -680,43 +680,43 @@ static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct r
__FUNCTION__, vertex_size, offset);
BEGIN_BATCH(7);
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
}
static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
{
BATCH_LOCALS(&rmesa->radeon);
int type, num_verts;
type = r300PrimitiveType(rmesa, primitive);
num_verts = r300NumVerts(rmesa, vertex_nr, primitive);
type = r600PrimitiveType(rmesa, primitive);
num_verts = r600NumVerts(rmesa, vertex_nr, primitive);
BEGIN_BATCH(3);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
END_BATCH();
}
void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
rcommonEnsureCmdBufSpace(&rmesa->radeon,
rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
__FUNCTION__);
radeonEmitState(&rmesa->radeon);
r300EmitVertexAOS(rmesa,
r600EmitVertexAOS(rmesa,
rmesa->radeon.swtcl.vertex_size,
rmesa->radeon.dma.current,
current_offset);
r300EmitVbufPrim(rmesa,
r600EmitVbufPrim(rmesa,
rmesa->radeon.swtcl.hw_primitive,
rmesa->radeon.swtcl.numverts);
r300EmitCacheFlush(rmesa);
r600EmitCacheFlush(rmesa);
COMMIT_BATCH();
}
src/mesa/drivers/dri/r600/r600_swtcl.h
+8 -8
View File
@@ -39,11 +39,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "swrast/swrast.h"
#include "r600_context.h"
#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
#define MASK_X R300_WRITE_ENA_X
#define MASK_Y R300_WRITE_ENA_Y
#define MASK_Z R300_WRITE_ENA_Z
#define MASK_W R300_WRITE_ENA_W
#define MASK_XYZW (R600_WRITE_ENA_X | R600_WRITE_ENA_Y | R600_WRITE_ENA_Z | R600_WRITE_ENA_W)
#define MASK_X R600_WRITE_ENA_X
#define MASK_Y R600_WRITE_ENA_Y
#define MASK_Z R600_WRITE_ENA_Z
#define MASK_W R600_WRITE_ENA_W
/*
* Here are definitions of OVM locations of vertex attributes for non TCL hw
@@ -55,8 +55,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define SWTCL_OVM_POINT_SIZE 15
extern void r300InitSwtcl( GLcontext *ctx );
extern void r300DestroySwtcl( GLcontext *ctx );
extern void r600InitSwtcl( GLcontext *ctx );
extern void r600DestroySwtcl( GLcontext *ctx );
extern void r300_swtcl_flush(GLcontext *ctx, uint32_t current_offset);
extern void r600_swtcl_flush(GLcontext *ctx, uint32_t current_offset);
#endif
src/mesa/drivers/dri/r600/r600_tex.c
+50 -50
View File
@@ -59,14 +59,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
static unsigned int translate_wrap_mode(GLenum wrapmode)
{
switch(wrapmode) {
case GL_REPEAT: return R300_TX_REPEAT;
case GL_CLAMP: return R300_TX_CLAMP;
case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE;
case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER;
case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED;
case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED;
case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED;
case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED;
case GL_REPEAT: return R600_TX_REPEAT;
case GL_CLAMP: return R600_TX_CLAMP;
case GL_CLAMP_TO_EDGE: return R600_TX_CLAMP_TO_EDGE;
case GL_CLAMP_TO_BORDER: return R600_TX_CLAMP_TO_BORDER;
case GL_MIRRORED_REPEAT: return R600_TX_REPEAT | R600_TX_MIRRORED;
case GL_MIRROR_CLAMP_EXT: return R600_TX_CLAMP | R600_TX_MIRRORED;
case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R600_TX_CLAMP_TO_EDGE | R600_TX_MIRRORED;
case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R600_TX_CLAMP_TO_BORDER | R600_TX_MIRRORED;
default:
_mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__);
return 0;
@@ -79,35 +79,35 @@ static unsigned int translate_wrap_mode(GLenum wrapmode)
*
* \param t Texture object whose wrap modes are to be set
*/
static void r300UpdateTexWrap(radeonTexObjPtr t)
static void r600UpdateTexWrap(radeonTexObjPtr t)
{
struct gl_texture_object *tObj = &t->base;
t->pp_txfilter &=
~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK);
~(R600_TX_WRAP_S_MASK | R600_TX_WRAP_T_MASK | R600_TX_WRAP_R_MASK);
t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R300_TX_WRAP_S_SHIFT;
t->pp_txfilter |= translate_wrap_mode(tObj->WrapS) << R600_TX_WRAP_S_SHIFT;
if (tObj->Target != GL_TEXTURE_1D) {
t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R300_TX_WRAP_T_SHIFT;
t->pp_txfilter |= translate_wrap_mode(tObj->WrapT) << R600_TX_WRAP_T_SHIFT;
if (tObj->Target == GL_TEXTURE_3D)
t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R300_TX_WRAP_R_SHIFT;
t->pp_txfilter |= translate_wrap_mode(tObj->WrapR) << R600_TX_WRAP_R_SHIFT;
}
}
static GLuint aniso_filter(GLfloat anisotropy)
{
if (anisotropy >= 16.0) {
return R300_TX_MAX_ANISO_16_TO_1;
return R600_TX_MAX_ANISO_16_TO_1;
} else if (anisotropy >= 8.0) {
return R300_TX_MAX_ANISO_8_TO_1;
return R600_TX_MAX_ANISO_8_TO_1;
} else if (anisotropy >= 4.0) {
return R300_TX_MAX_ANISO_4_TO_1;
return R600_TX_MAX_ANISO_4_TO_1;
} else if (anisotropy >= 2.0) {
return R300_TX_MAX_ANISO_2_TO_1;
return R600_TX_MAX_ANISO_2_TO_1;
} else {
return R300_TX_MAX_ANISO_1_TO_1;
return R600_TX_MAX_ANISO_1_TO_1;
}
}
@@ -119,13 +119,13 @@ static GLuint aniso_filter(GLfloat anisotropy)
* \param magf Texture magnification mode
* \param anisotropy Maximum anisotropy level
*/
static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
{
/* Force revalidation to account for switches from/to mipmapping. */
t->validated = GL_FALSE;
t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK);
t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY;
t->pp_txfilter &= ~(R600_TX_MIN_FILTER_MASK | R600_TX_MIN_FILTER_MIP_MASK | R600_TX_MAG_FILTER_MASK | R600_TX_MAX_ANISO_MASK);
t->pp_txfilter_1 &= ~R600_EDGE_ANISO_EDGE_ONLY;
/* Note that EXT_texture_filter_anisotropic is extremely vague about
* how anisotropic filtering interacts with the "normal" filter modes.
@@ -133,9 +133,9 @@ static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa
* filter settings completely. This includes driconf's settings.
*/
if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
| R300_TX_MIN_FILTER_ANISO
| R300_TX_MIN_FILTER_MIP_LINEAR
t->pp_txfilter |= R600_TX_MAG_FILTER_ANISO
| R600_TX_MIN_FILTER_ANISO
| R600_TX_MIN_FILTER_MIP_LINEAR
| aniso_filter(anisotropy);
if (RADEON_DEBUG & DEBUG_TEXTURE)
fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy);
@@ -144,22 +144,22 @@ static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa
switch (minf) {
case GL_NEAREST:
t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST;
t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST;
break;
case GL_LINEAR:
t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR;
t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR;
break;
case GL_NEAREST_MIPMAP_NEAREST:
t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST;
t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST|R600_TX_MIN_FILTER_MIP_NEAREST;
break;
case GL_NEAREST_MIPMAP_LINEAR:
t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR;
t->pp_txfilter |= R600_TX_MIN_FILTER_NEAREST|R600_TX_MIN_FILTER_MIP_LINEAR;
break;
case GL_LINEAR_MIPMAP_NEAREST:
t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST;
t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR|R600_TX_MIN_FILTER_MIP_NEAREST;
break;
case GL_LINEAR_MIPMAP_LINEAR:
t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR;
t->pp_txfilter |= R600_TX_MIN_FILTER_LINEAR|R600_TX_MIN_FILTER_MIP_LINEAR;
break;
}
@@ -168,15 +168,15 @@ static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa
*/
switch (magf) {
case GL_NEAREST:
t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST;
t->pp_txfilter |= R600_TX_MAG_FILTER_NEAREST;
break;
case GL_LINEAR:
t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR;
t->pp_txfilter |= R600_TX_MAG_FILTER_LINEAR;
break;
}
}
static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4])
static void r600SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4])
{
t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
}
@@ -186,7 +186,7 @@ static void r300SetTexBorderColor(radeonTexObjPtr t, GLubyte c[4])
* next UpdateTextureState
*/
static void r300TexParameter(GLcontext * ctx, GLenum target,
static void r600TexParameter(GLcontext * ctx, GLenum target,
struct gl_texture_object *texObj,
GLenum pname, const GLfloat * params)
{
@@ -201,17 +201,17 @@ static void r300TexParameter(GLcontext * ctx, GLenum target,
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
r300SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
r600SetTexFilter(t, texObj->MinFilter, texObj->MagFilter, texObj->MaxAnisotropy);
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
case GL_TEXTURE_WRAP_R:
r300UpdateTexWrap(t);
r600UpdateTexWrap(t);
break;
case GL_TEXTURE_BORDER_COLOR:
r300SetTexBorderColor(t, texObj->_BorderChan);
r600SetTexBorderColor(t, texObj->_BorderChan);
break;
case GL_TEXTURE_BASE_LEVEL:
@@ -235,7 +235,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target,
return;
if (texObj->Image[0][texObj->BaseLevel]->TexFormat->BaseFormat
== GL_DEPTH_COMPONENT) {
r300SetDepthTexMode(texObj);
r600SetDepthTexMode(texObj);
break;
} else {
/* If the texture isn't a depth texture, changing this
@@ -250,9 +250,9 @@ static void r300TexParameter(GLcontext * ctx, GLenum target,
}
}
static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
radeonTexObj* t = radeon_tex_obj(texObj);
if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) {
@@ -265,7 +265,7 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
int i;
radeon_firevertices(&rmesa->radeon);
for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i)
for(i = 0; i < R600_MAX_TEXTURE_UNITS; ++i)
if (rmesa->hw.textures[i] == t)
rmesa->hw.textures[i] = 0;
}
@@ -289,11 +289,11 @@ static void r300DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
* allocate the default texture objects.
* Fixup MaxAnisotropy according to user preference.
*/
static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx,
static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx,
GLuint name,
GLenum target)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
@@ -306,14 +306,14 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx,
t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
/* Initialize hardware state */
r300UpdateTexWrap(t);
r300SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
r300SetTexBorderColor(t, t->base._BorderChan);
r600UpdateTexWrap(t);
r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
r600SetTexBorderColor(t, t->base._BorderChan);
return &t->base;
}
void r300InitTextureFuncs(struct dd_function_table *functions)
void r600InitTextureFuncs(struct dd_function_table *functions)
{
/* Note: we only plug in the functions we implement in the driver
* since _mesa_init_driver_functions() was already called.
@@ -332,11 +332,11 @@ void r300InitTextureFuncs(struct dd_function_table *functions)
functions->TexSubImage3D = radeonTexSubImage3D;
functions->GetTexImage = radeonGetTexImage;
functions->GetCompressedTexImage = radeonGetCompressedTexImage;
functions->NewTextureObject = r300NewTextureObject;
functions->DeleteTexture = r300DeleteTexture;
functions->NewTextureObject = r600NewTextureObject;
functions->DeleteTexture = r600DeleteTexture;
functions->IsTextureResident = driIsTextureResident;
functions->TexParameter = r300TexParameter;
functions->TexParameter = r600TexParameter;
functions->CompressedTexImage2D = radeonCompressedTexImage2D;
functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D;
src/mesa/drivers/dri/r600/r600_tex.h
+6 -6
View File
@@ -35,20 +35,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef __r600_TEX_H__
#define __r600_TEX_H__
extern void r300SetDepthTexMode(struct gl_texture_object *tObj);
extern void r600SetDepthTexMode(struct gl_texture_object *tObj);
extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
extern void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
__DRIdrawable *dPriv);
extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
extern void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
GLint format, __DRIdrawable *dPriv);
extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
extern void r600SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
unsigned long long offset, GLint depth,
GLuint pitch);
extern GLboolean r300ValidateBuffers(GLcontext * ctx);
extern GLboolean r600ValidateBuffers(GLcontext * ctx);
extern void r300InitTextureFuncs(struct dd_function_table *functions);
extern void r600InitTextureFuncs(struct dd_function_table *functions);
#endif /* __r600_TEX_H__ */
src/mesa/drivers/dri/r600/r600_texstate.c
+84 -84
View File
@@ -32,7 +32,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*
* \todo Enable R300 texture tiling code?
* \todo Enable R600 texture tiling code?
*/
#include "main/glheader.h"
@@ -63,8 +63,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* Note that the _REV formats are the same as the non-REV formats. This is
* because the REV and non-REV formats are identical as a byte string, but
* differ when accessed as 16-bit or 32-bit words depending on the endianness of
* the host. Since the textures are transferred to the R300 as a byte string
* (i.e. without any byte-swapping), the R300 sees the REV and non-REV formats
* the host. Since the textures are transferred to the R600 as a byte string
* (i.e. without any byte-swapping), the R600 sees the REV and non-REV formats
* identically. -- paulus
*/
@@ -73,73 +73,73 @@ static const struct tx_table {
} tx_table[] = {
/* *INDENT-OFF* */
#ifdef MESA_LITTLE_ENDIAN
_ASSIGN(RGBA8888, R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
_ASSIGN(RGBA8888_REV, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
_ASSIGN(ARGB8888, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
_ASSIGN(ARGB8888_REV, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
_ASSIGN(RGBA8888, R600_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
_ASSIGN(RGBA8888_REV, R600_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
_ASSIGN(ARGB8888, R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
_ASSIGN(ARGB8888_REV, R600_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
#else
_ASSIGN(RGBA8888, R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
_ASSIGN(RGBA8888_REV, R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
_ASSIGN(ARGB8888, R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
_ASSIGN(ARGB8888_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
_ASSIGN(RGBA8888, R600_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8)),
_ASSIGN(RGBA8888_REV, R600_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8)),
_ASSIGN(ARGB8888, R600_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8)),
_ASSIGN(ARGB8888_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8)),
#endif
_ASSIGN(RGB888, R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)),
_ASSIGN(RGB565, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
_ASSIGN(RGB565_REV, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
_ASSIGN(ARGB4444, R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
_ASSIGN(ARGB4444_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
_ASSIGN(ARGB1555, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
_ASSIGN(ARGB1555_REV, R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
_ASSIGN(AL88, R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
_ASSIGN(AL88_REV, R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
_ASSIGN(RGB332, R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2)),
_ASSIGN(A8, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)),
_ASSIGN(L8, R300_EASY_TX_FORMAT(X, X, X, ONE, X8)),
_ASSIGN(I8, R300_EASY_TX_FORMAT(X, X, X, X, X8)),
_ASSIGN(CI8, R300_EASY_TX_FORMAT(X, X, X, X, X8)),
_ASSIGN(YCBCR, R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE),
_ASSIGN(YCBCR_REV, R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE),
_ASSIGN(RGB_DXT1, R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1)),
_ASSIGN(RGBA_DXT1, R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1)),
_ASSIGN(RGBA_DXT3, R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3)),
_ASSIGN(RGBA_DXT5, R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5)),
_ASSIGN(RGBA_FLOAT32, R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32)),
_ASSIGN(RGBA_FLOAT16, R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16)),
_ASSIGN(RGB888, R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8)),
_ASSIGN(RGB565, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
_ASSIGN(RGB565_REV, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5)),
_ASSIGN(ARGB4444, R600_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
_ASSIGN(ARGB4444_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4)),
_ASSIGN(ARGB1555, R600_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
_ASSIGN(ARGB1555_REV, R600_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5)),
_ASSIGN(AL88, R600_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
_ASSIGN(AL88_REV, R600_EASY_TX_FORMAT(X, X, X, Y, Y8X8)),
_ASSIGN(RGB332, R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2)),
_ASSIGN(A8, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8)),
_ASSIGN(L8, R600_EASY_TX_FORMAT(X, X, X, ONE, X8)),
_ASSIGN(I8, R600_EASY_TX_FORMAT(X, X, X, X, X8)),
_ASSIGN(CI8, R600_EASY_TX_FORMAT(X, X, X, X, X8)),
_ASSIGN(YCBCR, R600_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R600_TX_FORMAT_YUV_MODE),
_ASSIGN(YCBCR_REV, R600_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R600_TX_FORMAT_YUV_MODE),
_ASSIGN(RGB_DXT1, R600_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1)),
_ASSIGN(RGBA_DXT1, R600_EASY_TX_FORMAT(X, Y, Z, W, DXT1)),
_ASSIGN(RGBA_DXT3, R600_EASY_TX_FORMAT(X, Y, Z, W, DXT3)),
_ASSIGN(RGBA_DXT5, R600_EASY_TX_FORMAT(Y, Z, W, X, DXT5)),
_ASSIGN(RGBA_FLOAT32, R600_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32)),
_ASSIGN(RGBA_FLOAT16, R600_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16)),
_ASSIGN(RGB_FLOAT32, 0xffffffff),
_ASSIGN(RGB_FLOAT16, 0xffffffff),
_ASSIGN(ALPHA_FLOAT32, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32)),
_ASSIGN(ALPHA_FLOAT16, R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16)),
_ASSIGN(LUMINANCE_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I32)),
_ASSIGN(LUMINANCE_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I16)),
_ASSIGN(LUMINANCE_ALPHA_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32)),
_ASSIGN(LUMINANCE_ALPHA_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16)),
_ASSIGN(INTENSITY_FLOAT32, R300_EASY_TX_FORMAT(X, X, X, X, FL_I32)),
_ASSIGN(INTENSITY_FLOAT16, R300_EASY_TX_FORMAT(X, X, X, X, FL_I16)),
_ASSIGN(Z16, R300_EASY_TX_FORMAT(X, X, X, X, X16)),
_ASSIGN(Z24_S8, R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8)),
_ASSIGN(Z32, R300_EASY_TX_FORMAT(X, X, X, X, X32)),
_ASSIGN(ALPHA_FLOAT32, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32)),
_ASSIGN(ALPHA_FLOAT16, R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16)),
_ASSIGN(LUMINANCE_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, ONE, FL_I32)),
_ASSIGN(LUMINANCE_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, ONE, FL_I16)),
_ASSIGN(LUMINANCE_ALPHA_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32)),
_ASSIGN(LUMINANCE_ALPHA_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16)),
_ASSIGN(INTENSITY_FLOAT32, R600_EASY_TX_FORMAT(X, X, X, X, FL_I32)),
_ASSIGN(INTENSITY_FLOAT16, R600_EASY_TX_FORMAT(X, X, X, X, FL_I16)),
_ASSIGN(Z16, R600_EASY_TX_FORMAT(X, X, X, X, X16)),
_ASSIGN(Z24_S8, R600_EASY_TX_FORMAT(X, X, X, X, X24_Y8)),
_ASSIGN(Z32, R600_EASY_TX_FORMAT(X, X, X, X, X32)),
/* *INDENT-ON* */
};
#undef _ASSIGN
void r300SetDepthTexMode(struct gl_texture_object *tObj)
void r600SetDepthTexMode(struct gl_texture_object *tObj)
{
static const GLuint formats[3][3] = {
{
R300_EASY_TX_FORMAT(X, X, X, ONE, X16),
R300_EASY_TX_FORMAT(X, X, X, X, X16),
R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16),
R600_EASY_TX_FORMAT(X, X, X, ONE, X16),
R600_EASY_TX_FORMAT(X, X, X, X, X16),
R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16),
},
{
R300_EASY_TX_FORMAT(X, X, X, ONE, X24_Y8),
R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8),
R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X24_Y8),
R600_EASY_TX_FORMAT(X, X, X, ONE, X24_Y8),
R600_EASY_TX_FORMAT(X, X, X, X, X24_Y8),
R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X24_Y8),
},
{
R300_EASY_TX_FORMAT(X, X, X, ONE, X32),
R300_EASY_TX_FORMAT(X, X, X, X, X32),
R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32),
R600_EASY_TX_FORMAT(X, X, X, ONE, X32),
R600_EASY_TX_FORMAT(X, X, X, X, X32),
R600_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32),
},
};
const GLuint *format;
@@ -192,9 +192,9 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj)
* Compute the cached hardware register values for the given texture object.
*
* \param rmesa Context pointer
* \param t the r300 texture object
* \param t the r600 texture object
*/
static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
static void setup_hardware_state(r600ContextPtr rmesa, radeonTexObj *t)
{
const struct gl_texture_image *firstImage;
int firstlevel = t->mt ? t->mt->firstLevel : 0;
@@ -204,7 +204,7 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
if (!t->image_override
&& VALID_FORMAT(firstImage->TexFormat->MesaFormat)) {
if (firstImage->TexFormat->BaseFormat == GL_DEPTH_COMPONENT) {
r300SetDepthTexMode(&t->base);
r600SetDepthTexMode(&t->base);
} else {
t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format;
}
@@ -219,22 +219,22 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
if (t->image_override && t->bo)
return;
t->pp_txsize = (((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)
| ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)
| ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)
| ((t->mt->lastLevel - t->mt->firstLevel) << R300_TX_MAX_MIP_LEVEL_SHIFT));
t->pp_txsize = (((firstImage->Width - 1) << R600_TX_WIDTHMASK_SHIFT)
| ((firstImage->Height - 1) << R600_TX_HEIGHTMASK_SHIFT)
| ((firstImage->DepthLog2) << R600_TX_DEPTHMASK_SHIFT)
| ((t->mt->lastLevel - t->mt->firstLevel) << R600_TX_MAX_MIP_LEVEL_SHIFT));
t->tile_bits = 0;
if (t->base.Target == GL_TEXTURE_CUBE_MAP)
t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP;
t->pp_txformat |= R600_TX_FORMAT_CUBIC_MAP;
if (t->base.Target == GL_TEXTURE_3D)
t->pp_txformat |= R300_TX_FORMAT_3D;
t->pp_txformat |= R600_TX_FORMAT_3D;
if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
unsigned int align = (64 / t->mt->bpp) - 1;
t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN;
if (!t->image_override)
t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1;
}
@@ -252,9 +252,9 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
*
* Mostly this means populating the texture object's mipmap tree.
*/
static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj)
static GLboolean r600_validate_texture(GLcontext * ctx, struct gl_texture_object *texObj)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
if (!radeon_validate_texture_miptree(ctx, texObj))
@@ -271,9 +271,9 @@ static GLboolean r300_validate_texture(GLcontext * ctx, struct gl_texture_object
/**
* Ensure all enabled and complete textures are uploaded along with any buffers being used.
*/
GLboolean r300ValidateBuffers(GLcontext * ctx)
GLboolean r600ValidateBuffers(GLcontext * ctx)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r600ContextPtr rmesa = R600_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
int i;
@@ -299,7 +299,7 @@ GLboolean r300ValidateBuffers(GLcontext * ctx)
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
_mesa_warning(ctx,
"failed to validate texture for unit %d.\n",
i);
@@ -319,10 +319,10 @@ GLboolean r300ValidateBuffers(GLcontext * ctx)
return radeon_revalidate_bos(ctx);
}
void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
unsigned long long offset, GLint depth, GLuint pitch)
{
r300ContextPtr rmesa = pDRICtx->driverPrivate;
r600ContextPtr rmesa = pDRICtx->driverPrivate;
struct gl_texture_object *tObj =
_mesa_lookup_texture(rmesa->radeon.glCtx, texname);
radeonTexObjPtr t = radeon_tex_obj(tObj);
@@ -343,18 +343,18 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
switch (depth) {
case 32:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
t->pp_txfilter |= tx_table[2].filter;
pitch_val /= 4;
break;
case 24:
default:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
t->pp_txfilter |= tx_table[4].filter;
pitch_val /= 4;
break;
case 16:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
t->pp_txfilter |= tx_table[5].filter;
pitch_val /= 2;
break;
@@ -364,7 +364,7 @@ void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
t->pp_txpitch |= pitch_val;
}
void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv)
{
struct gl_texture_unit *texUnit;
struct gl_texture_object *texObj;
@@ -372,7 +372,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
struct radeon_renderbuffer *rb;
radeon_texture_image *rImage;
radeonContextPtr radeon;
r300ContextPtr rmesa;
r600ContextPtr rmesa;
struct radeon_framebuffer *rfb;
radeonTexObjPtr t;
uint32_t pitch_val;
@@ -449,26 +449,26 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
pitch_val = rb->pitch;
switch (rb->cpp) {
case 4:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
t->pp_txfilter |= tx_table[2].filter;
pitch_val /= 4;
break;
case 3:
default:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
t->pp_txfilter |= tx_table[4].filter;
pitch_val /= 4;
break;
case 2:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
t->pp_txformat = R600_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
t->pp_txfilter |= tx_table[5].filter;
pitch_val /= 2;
break;
}
pitch_val--;
t->pp_txsize = ((rb->width - 1) << R300_TX_WIDTHMASK_SHIFT) |
((rb->height - 1) << R300_TX_HEIGHTMASK_SHIFT);
t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
t->pp_txsize = ((rb->width - 1) << R600_TX_WIDTHMASK_SHIFT) |
((rb->height - 1) << R600_TX_HEIGHTMASK_SHIFT);
t->pp_txsize |= R600_TX_SIZE_TXPITCH_EN;
t->pp_txpitch |= pitch_val;
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
@@ -482,7 +482,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
return;
}
void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
void r600SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
{
r300SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
r600SetTexBuffer2(pDRICtx, target, GLX_TEXTURE_FORMAT_RGBA_EXT, dPriv);
}
src/mesa/drivers/dri/r600/r600_vertprog.c
+79 -79
View File
@@ -69,8 +69,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
u_temp_i=VSF_MAX_FRAGMENT_TEMPS-1; \
} while (0)
int r300VertexProgUpdateParams(GLcontext * ctx,
struct r300_vertex_program_cont *vp, float *dst)
int r600VertexProgUpdateParams(GLcontext * ctx,
struct r600_vertex_program_cont *vp, float *dst)
{
int pi;
struct gl_vertex_program *mesa_vp = &vp->mesa_program;
@@ -152,7 +152,7 @@ static unsigned long t_dst_class(gl_register_file file)
}
}
static unsigned long t_dst_index(struct r300_vertex_program *vp,
static unsigned long t_dst_index(struct r600_vertex_program *vp,
struct prog_dst_register *dst)
{
if (dst->File == PROGRAM_OUTPUT)
@@ -193,7 +193,7 @@ static INLINE unsigned long t_swizzle(GLubyte swizzle)
}
#if 0
static void vp_dump_inputs(struct r300_vertex_program *vp, char *caller)
static void vp_dump_inputs(struct r600_vertex_program *vp, char *caller)
{
int i;
@@ -211,7 +211,7 @@ static void vp_dump_inputs(struct r300_vertex_program *vp, char *caller)
}
#endif
static unsigned long t_src_index(struct r300_vertex_program *vp,
static unsigned long t_src_index(struct r600_vertex_program *vp,
struct prog_src_register *src)
{
int i;
@@ -242,7 +242,7 @@ static unsigned long t_src_index(struct r300_vertex_program *vp,
/* these two functions should probably be merged... */
static unsigned long t_src(struct r300_vertex_program *vp,
static unsigned long t_src(struct r600_vertex_program *vp,
struct prog_src_register *src)
{
/* src->NegateBase uses the NEGATE_ flags from program_instruction.h,
@@ -257,7 +257,7 @@ static unsigned long t_src(struct r300_vertex_program *vp,
src->NegateBase) | (src->RelAddr << 4);
}
static unsigned long t_src_scalar(struct r300_vertex_program *vp,
static unsigned long t_src_scalar(struct r600_vertex_program *vp,
struct prog_src_register *src)
{
/* src->NegateBase uses the NEGATE_ flags from program_instruction.h,
@@ -274,7 +274,7 @@ static unsigned long t_src_scalar(struct r300_vertex_program *vp,
(src->RelAddr << 4);
}
static GLboolean valid_dst(struct r300_vertex_program *vp,
static GLboolean valid_dst(struct r600_vertex_program *vp,
struct prog_dst_register *dst)
{
if (dst->File == PROGRAM_OUTPUT && vp->outputs[dst->Index] == -1) {
@@ -286,7 +286,7 @@ static GLboolean valid_dst(struct r300_vertex_program *vp,
return GL_TRUE;
}
static GLuint *r300TranslateOpcodeABS(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeABS(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -314,7 +314,7 @@ static GLuint *r300TranslateOpcodeABS(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeADD(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeADD(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -332,7 +332,7 @@ static GLuint *r300TranslateOpcodeADD(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeARL(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeARL(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -350,7 +350,7 @@ static GLuint *r300TranslateOpcodeARL(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeDP3(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeDP3(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -386,7 +386,7 @@ static GLuint *r300TranslateOpcodeDP3(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeDP4(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeDP4(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -404,7 +404,7 @@ static GLuint *r300TranslateOpcodeDP4(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeDPH(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeDPH(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -431,7 +431,7 @@ static GLuint *r300TranslateOpcodeDPH(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeDST(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeDST(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -449,7 +449,7 @@ static GLuint *r300TranslateOpcodeDST(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeEX2(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeEX2(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -467,7 +467,7 @@ static GLuint *r300TranslateOpcodeEX2(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeEXP(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeEXP(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -485,7 +485,7 @@ static GLuint *r300TranslateOpcodeEXP(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeFLR(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeFLR(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3],
@@ -527,7 +527,7 @@ static GLuint *r300TranslateOpcodeFLR(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeFRC(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeFRC(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -545,7 +545,7 @@ static GLuint *r300TranslateOpcodeFRC(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeLG2(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeLG2(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -573,7 +573,7 @@ static GLuint *r300TranslateOpcodeLG2(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeLIT(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeLIT(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -615,7 +615,7 @@ static GLuint *r300TranslateOpcodeLIT(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeLOG(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeLOG(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -633,7 +633,7 @@ static GLuint *r300TranslateOpcodeLOG(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeMAD(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeMAD(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -651,7 +651,7 @@ static GLuint *r300TranslateOpcodeMAD(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeMAX(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeMAX(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -669,7 +669,7 @@ static GLuint *r300TranslateOpcodeMAX(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeMIN(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeMIN(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -687,7 +687,7 @@ static GLuint *r300TranslateOpcodeMIN(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeMOV(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -707,7 +707,7 @@ static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeMUL(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeMUL(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -725,7 +725,7 @@ static GLuint *r300TranslateOpcodeMUL(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodePOW(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodePOW(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -743,7 +743,7 @@ static GLuint *r300TranslateOpcodePOW(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeRCP(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeRCP(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -761,7 +761,7 @@ static GLuint *r300TranslateOpcodeRCP(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeRSQ(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeRSQ(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -779,7 +779,7 @@ static GLuint *r300TranslateOpcodeRSQ(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeSGE(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeSGE(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -797,7 +797,7 @@ static GLuint *r300TranslateOpcodeSGE(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeSLT(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeSLT(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -815,7 +815,7 @@ static GLuint *r300TranslateOpcodeSLT(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeSUB(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeSUB(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -864,7 +864,7 @@ static GLuint *r300TranslateOpcodeSUB(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeSWZ(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeSWZ(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
@@ -884,7 +884,7 @@ static GLuint *r300TranslateOpcodeSWZ(struct r300_vertex_program *vp,
return inst;
}
static GLuint *r300TranslateOpcodeXPD(struct r300_vertex_program *vp,
static GLuint *r600TranslateOpcodeXPD(struct r600_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3],
@@ -951,7 +951,7 @@ static GLuint *r300TranslateOpcodeXPD(struct r300_vertex_program *vp,
return inst;
}
static void t_inputs_outputs(struct r300_vertex_program *vp)
static void t_inputs_outputs(struct r600_vertex_program *vp)
{
int i;
int cur_reg = 0;
@@ -1005,14 +1005,14 @@ static void t_inputs_outputs(struct r300_vertex_program *vp)
}
}
static void r300TranslateVertexShader(struct r300_vertex_program *vp,
static void r600TranslateVertexShader(struct r600_vertex_program *vp,
struct prog_instruction *vpi)
{
int i;
GLuint *inst;
unsigned long num_operands;
/* Initial value should be last tmp reg that hw supports.
Strangely enough r300 doesnt mind even though these would be out of range.
Strangely enough r600 doesnt mind even though these would be out of range.
Smart enough to realize that it doesnt need it? */
int u_temp_i = VSF_MAX_FRAGMENT_TEMPS - 1;
struct prog_src_register src[3];
@@ -1104,86 +1104,86 @@ static void r300TranslateVertexShader(struct r300_vertex_program *vp,
switch (vpi->Opcode) {
case OPCODE_ABS:
inst = r300TranslateOpcodeABS(vp, vpi, inst, src);
inst = r600TranslateOpcodeABS(vp, vpi, inst, src);
break;
case OPCODE_ADD:
inst = r300TranslateOpcodeADD(vp, vpi, inst, src);
inst = r600TranslateOpcodeADD(vp, vpi, inst, src);
break;
case OPCODE_ARL:
inst = r300TranslateOpcodeARL(vp, vpi, inst, src);
inst = r600TranslateOpcodeARL(vp, vpi, inst, src);
break;
case OPCODE_DP3:
inst = r300TranslateOpcodeDP3(vp, vpi, inst, src);
inst = r600TranslateOpcodeDP3(vp, vpi, inst, src);
break;
case OPCODE_DP4:
inst = r300TranslateOpcodeDP4(vp, vpi, inst, src);
inst = r600TranslateOpcodeDP4(vp, vpi, inst, src);
break;
case OPCODE_DPH:
inst = r300TranslateOpcodeDPH(vp, vpi, inst, src);
inst = r600TranslateOpcodeDPH(vp, vpi, inst, src);
break;
case OPCODE_DST:
inst = r300TranslateOpcodeDST(vp, vpi, inst, src);
inst = r600TranslateOpcodeDST(vp, vpi, inst, src);
break;
case OPCODE_EX2:
inst = r300TranslateOpcodeEX2(vp, vpi, inst, src);
inst = r600TranslateOpcodeEX2(vp, vpi, inst, src);
break;
case OPCODE_EXP:
inst = r300TranslateOpcodeEXP(vp, vpi, inst, src);
inst = r600TranslateOpcodeEXP(vp, vpi, inst, src);
break;
case OPCODE_FLR:
inst = r300TranslateOpcodeFLR(vp, vpi, inst, src, /* FIXME */
inst = r600TranslateOpcodeFLR(vp, vpi, inst, src, /* FIXME */
&u_temp_i);
break;
case OPCODE_FRC:
inst = r300TranslateOpcodeFRC(vp, vpi, inst, src);
inst = r600TranslateOpcodeFRC(vp, vpi, inst, src);
break;
case OPCODE_LG2:
inst = r300TranslateOpcodeLG2(vp, vpi, inst, src);
inst = r600TranslateOpcodeLG2(vp, vpi, inst, src);
break;
case OPCODE_LIT:
inst = r300TranslateOpcodeLIT(vp, vpi, inst, src);
inst = r600TranslateOpcodeLIT(vp, vpi, inst, src);
break;
case OPCODE_LOG:
inst = r300TranslateOpcodeLOG(vp, vpi, inst, src);
inst = r600TranslateOpcodeLOG(vp, vpi, inst, src);
break;
case OPCODE_MAD:
inst = r300TranslateOpcodeMAD(vp, vpi, inst, src);
inst = r600TranslateOpcodeMAD(vp, vpi, inst, src);
break;
case OPCODE_MAX:
inst = r300TranslateOpcodeMAX(vp, vpi, inst, src);
inst = r600TranslateOpcodeMAX(vp, vpi, inst, src);
break;
case OPCODE_MIN:
inst = r300TranslateOpcodeMIN(vp, vpi, inst, src);
inst = r600TranslateOpcodeMIN(vp, vpi, inst, src);
break;
case OPCODE_MOV:
inst = r300TranslateOpcodeMOV(vp, vpi, inst, src);
inst = r600TranslateOpcodeMOV(vp, vpi, inst, src);
break;
case OPCODE_MUL:
inst = r300TranslateOpcodeMUL(vp, vpi, inst, src);
inst = r600TranslateOpcodeMUL(vp, vpi, inst, src);
break;
case OPCODE_POW:
inst = r300TranslateOpcodePOW(vp, vpi, inst, src);
inst = r600TranslateOpcodePOW(vp, vpi, inst, src);
break;
case OPCODE_RCP:
inst = r300TranslateOpcodeRCP(vp, vpi, inst, src);
inst = r600TranslateOpcodeRCP(vp, vpi, inst, src);
break;
case OPCODE_RSQ:
inst = r300TranslateOpcodeRSQ(vp, vpi, inst, src);
inst = r600TranslateOpcodeRSQ(vp, vpi, inst, src);
break;
case OPCODE_SGE:
inst = r300TranslateOpcodeSGE(vp, vpi, inst, src);
inst = r600TranslateOpcodeSGE(vp, vpi, inst, src);
break;
case OPCODE_SLT:
inst = r300TranslateOpcodeSLT(vp, vpi, inst, src);
inst = r600TranslateOpcodeSLT(vp, vpi, inst, src);
break;
case OPCODE_SUB:
inst = r300TranslateOpcodeSUB(vp, vpi, inst, src);
inst = r600TranslateOpcodeSUB(vp, vpi, inst, src);
break;
case OPCODE_SWZ:
inst = r300TranslateOpcodeSWZ(vp, vpi, inst, src);
inst = r600TranslateOpcodeSWZ(vp, vpi, inst, src);
break;
case OPCODE_XPD:
inst = r300TranslateOpcodeXPD(vp, vpi, inst, src, /* FIXME */
inst = r600TranslateOpcodeXPD(vp, vpi, inst, src, /* FIXME */
&u_temp_i);
break;
default:
@@ -1309,7 +1309,7 @@ static void position_invariant(struct gl_program *prog)
assert(vpi->Opcode == OPCODE_END);
}
static void insert_wpos(struct r300_vertex_program *vp, struct gl_program *prog,
static void insert_wpos(struct r600_vertex_program *vp, struct gl_program *prog,
GLuint temp_index)
{
struct prog_instruction *vpi;
@@ -1361,7 +1361,7 @@ static void insert_wpos(struct r300_vertex_program *vp, struct gl_program *prog,
assert(vpi->Opcode == OPCODE_END);
}
static void pos_as_texcoord(struct r300_vertex_program *vp,
static void pos_as_texcoord(struct r600_vertex_program *vp,
struct gl_program *prog)
{
struct prog_instruction *vpi;
@@ -1379,11 +1379,11 @@ static void pos_as_texcoord(struct r300_vertex_program *vp,
insert_wpos(vp, prog, tempregi);
}
static struct r300_vertex_program *build_program(struct r300_vertex_program_key
static struct r600_vertex_program *build_program(struct r600_vertex_program_key
*wanted_key, struct gl_vertex_program
*mesa_vp, GLint wpos_idx)
{
struct r300_vertex_program *vp;
struct r600_vertex_program *vp;
vp = _mesa_calloc(sizeof(*vp));
_mesa_memcpy(&vp->key, wanted_key, sizeof(vp->key));
@@ -1399,12 +1399,12 @@ static struct r300_vertex_program *build_program(struct r300_vertex_program_key
assert(mesa_vp->Base.NumInstructions);
vp->num_temporaries = mesa_vp->Base.NumTemporaries;
r300TranslateVertexShader(vp, mesa_vp->Base.Instructions);
r600TranslateVertexShader(vp, mesa_vp->Base.Instructions);
return vp;
}
static void add_outputs(struct r300_vertex_program_key *key, GLint vert)
static void add_outputs(struct r600_vertex_program_key *key, GLint vert)
{
if (key->OutputsWritten & (1 << vert))
return;
@@ -1413,17 +1413,17 @@ static void add_outputs(struct r300_vertex_program_key *key, GLint vert)
key->OutputsAdded |= 1 << vert;
}
void r300SelectVertexShader(r300ContextPtr r300)
void r600SelectVertexShader(r600ContextPtr r600)
{
GLcontext *ctx = ctx = r300->radeon.glCtx;
GLcontext *ctx = ctx = r600->radeon.glCtx;
GLuint InputsRead;
struct r300_vertex_program_key wanted_key = { 0 };
struct r600_vertex_program_key wanted_key = { 0 };
GLint i;
struct r300_vertex_program_cont *vpc;
struct r300_vertex_program *vp;
struct r600_vertex_program_cont *vpc;
struct r600_vertex_program *vp;
GLint wpos_idx;
vpc = (struct r300_vertex_program_cont *)ctx->VertexProgram._Current;
vpc = (struct r600_vertex_program_cont *)ctx->VertexProgram._Current;
wanted_key.InputsRead = vpc->mesa_program.Base.InputsRead;
wanted_key.OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
InputsRead = ctx->FragmentProgram._Current->Base.InputsRead;
@@ -1467,7 +1467,7 @@ void r300SelectVertexShader(r300ContextPtr r300)
for (vp = vpc->progs; vp; vp = vp->next)
if (_mesa_memcmp(&vp->key, &wanted_key, sizeof(wanted_key))
== 0) {
r300->selected_vp = vp;
r600->selected_vp = vp;
return;
}
//_mesa_print_program(&vpc->mesa_program.Base);
@@ -1475,5 +1475,5 @@ void r300SelectVertexShader(r300ContextPtr r300)
vp = build_program(&wanted_key, &vpc->mesa_program, wpos_idx);
vp->next = vpc->progs;
vpc->progs = vp;
r300->selected_vp = vp;
r600->selected_vp = vp;
}
src/mesa/drivers/dri/r600/r700_fragprog.c
+14 -14
View File
@@ -189,13 +189,13 @@ static GLboolean transform_TEX(
}
static void update_params(r300ContextPtr r300, struct r500_fragment_program *fp)
static void update_params(r600ContextPtr r600, struct r500_fragment_program *fp)
{
struct gl_fragment_program *mp = &fp->mesa_program;
/* Ask Mesa nicely to fill in ParameterValues for us */
if (mp->Base.Parameters)
_mesa_load_state_parameters(r300->radeon.glCtx, mp->Base.Parameters);
_mesa_load_state_parameters(r600->radeon.glCtx, mp->Base.Parameters);
}
@@ -218,7 +218,7 @@ static void insert_WPOS_trailer(struct r500_fragment_program_compiler *compiler)
return;
static gl_state_index tokens[STATE_LENGTH] = {
STATE_INTERNAL, STATE_R300_WINDOW_DIMENSION, 0, 0, 0
STATE_INTERNAL, STATE_R600_WINDOW_DIMENSION, 0, 0, 0
};
struct prog_instruction *fpi;
GLuint window_index;
@@ -419,7 +419,7 @@ static GLuint build_func(GLuint comparefunc)
* fragment program.
*/
static void build_state(
r300ContextPtr r300,
r600ContextPtr r600,
struct r500_fragment_program *fp,
struct r500_fragment_program_external_state *state)
{
@@ -429,7 +429,7 @@ static void build_state(
for(unit = 0; unit < 16; ++unit) {
if (fp->mesa_program.Base.ShadowSamplers & (1 << unit)) {
struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
struct gl_texture_object* tex = r600->radeon.glCtx->Texture.Unit[unit]._Current;
state->unit[unit].depth_texture_mode = build_dtm(tex->DepthMode);
state->unit[unit].texture_compare_func = build_func(tex->CompareFunc);
@@ -439,12 +439,12 @@ static void build_state(
static void dump_program(struct r500_fragment_program_code *code);
void r500TranslateFragmentShader(r300ContextPtr r300,
void r500TranslateFragmentShader(r600ContextPtr r600,
struct r500_fragment_program *fp)
{
struct r500_fragment_program_external_state state;
build_state(r300, fp, &state);
build_state(r600, fp, &state);
if (_mesa_memcmp(&fp->state, &state, sizeof(state))) {
/* TODO: cache compiled programs */
fp->translated = GL_FALSE;
@@ -454,10 +454,10 @@ void r500TranslateFragmentShader(r300ContextPtr r300,
if (!fp->translated) {
struct r500_fragment_program_compiler compiler;
compiler.r300 = r300;
compiler.r600 = r600;
compiler.fp = fp;
compiler.code = &fp->code;
compiler.program = _mesa_clone_program(r300->radeon.glCtx, &fp->mesa_program.Base);
compiler.program = _mesa_clone_program(r600->radeon.glCtx, &fp->mesa_program.Base);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: Initial program:\n");
@@ -472,7 +472,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300,
{ &radeonTransformDeriv, 0 },
{ &radeonTransformTrigScale, 0 }
};
radeonLocalTransform(r300->radeon.glCtx, compiler.program,
radeonLocalTransform(r600->radeon.glCtx, compiler.program,
4, transformations);
if (RADEON_DEBUG & DEBUG_PIXEL) {
@@ -486,7 +486,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300,
.BuildSwizzle = &nqssadce_build_swizzle,
.RewriteDepthOut = GL_TRUE
};
radeonNqssaDce(r300->radeon.glCtx, compiler.program, &nqssadce);
radeonNqssaDce(r600->radeon.glCtx, compiler.program, &nqssadce);
if (RADEON_DEBUG & DEBUG_PIXEL) {
_mesa_printf("Compiler: after NqSSA-DCE:\n");
@@ -500,9 +500,9 @@ void r500TranslateFragmentShader(r300ContextPtr r300,
fp->mesa_program.Base.Parameters = compiler.program->Parameters;
compiler.program->Parameters = 0;
_mesa_reference_program(r300->radeon.glCtx, &compiler.program, 0);
_mesa_reference_program(r600->radeon.glCtx, &compiler.program, 0);
r300UpdateStateParameters(r300->radeon.glCtx, _NEW_PROGRAM);
r600UpdateStateParameters(r600->radeon.glCtx, _NEW_PROGRAM);
if (RADEON_DEBUG & DEBUG_PIXEL) {
if (fp->translated) {
@@ -513,7 +513,7 @@ void r500TranslateFragmentShader(r300ContextPtr r300,
}
update_params(r300, fp);
update_params(r600, fp);
}
src/mesa/drivers/dri/r600/r700_fragprog.h
+2 -2
View File
@@ -47,11 +47,11 @@
struct r500_fragment_program;
extern void r500TranslateFragmentShader(r300ContextPtr r300,
extern void r500TranslateFragmentShader(r600ContextPtr r600,
struct r500_fragment_program *fp);
struct r500_fragment_program_compiler {
r300ContextPtr r300;
r600ContextPtr r600;
struct r500_fragment_program *fp;
struct r500_fragment_program_code *code;
struct gl_program *program;
src/mesa/drivers/dri/r600/r700_fragprog_emit.c
+1 -1
View File
@@ -308,7 +308,7 @@ GLboolean r500FragmentProgramEmit(struct r500_fragment_program_compiler *compile
code->inst_offset = 0;
code->inst_end = -1;
if (!radeonPairProgram(compiler->r300->radeon.glCtx, compiler->program, &pair_handler, compiler))
if (!radeonPairProgram(compiler->r600->radeon.glCtx, compiler->program, &pair_handler, compiler))
return GL_FALSE;
if ((code->inst[code->inst_end].inst0 & R500_INST_TYPE_MASK) != R500_INST_TYPE_OUT) {
src/mesa/drivers/dri/radeon/radeon_screen.c
+8 -8
View File
@@ -398,15 +398,15 @@ static const __DRItexBufferExtension r300TexBufferExtension = {
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
static const __DRItexOffsetExtension r300texOffsetExtension = {
static const __DRItexOffsetExtension r600texOffsetExtension = {
{ __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
r300SetTexOffset,
r600SetTexOffset,
};
static const __DRItexBufferExtension r300TexBufferExtension = {
static const __DRItexBufferExtension r600TexBufferExtension = {
{ __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
r300SetTexBuffer,
r300SetTexBuffer2,
r600SetTexBuffer,
r600SetTexBuffer2,
};
#endif
@@ -1201,7 +1201,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
screen->extensions[i++] = &r300texOffsetExtension.base;
screen->extensions[i++] = &r600texOffsetExtension.base;
#endif
}
@@ -1334,7 +1334,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv)
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
screen->extensions[i++] = &r300TexBufferExtension.base;
screen->extensions[i++] = &r600TexBufferExtension.base;
#endif
screen->extensions[i++] = NULL;
@@ -1532,7 +1532,7 @@ static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
if (IS_R600_CLASS(screen))
return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
return r600CreateContext(glVisual, driContextPriv, sharedContextPriv);
#endif
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)