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r600: Typos and whitespace fixes

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Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Jan Vesely
2016-01-21 11:17:28 -05:00
committed by Marek Olšák
parent 2924ca131f
commit e1dcd333e4
3 changed files with 7 additions and 7 deletions
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src/gallium/drivers/r600/evergreen_compute.c
+3 -3
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@@ -723,7 +723,7 @@ static void evergreen_set_global_binding(
* command stream by the start_cs_cmd atom. However, since the SET_CONTEXT_REG
* packet requires that the shader type bit be set, we must initialize all
* context registers needed for compute in this function. The registers
* intialized by the start_cs_cmd atom can be found in evereen_state.c in the
* initialized by the start_cs_cmd atom can be found in evergreen_state.c in the
* functions evergreen_init_atom_start_cs or cayman_init_atom_start_cs depending
* on the GPU family.
*/
@@ -733,7 +733,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
int num_threads;
int num_stack_entries;
/* since all required registers are initialised in the
/* since all required registers are initialized in the
* start_compute_cs_cmd atom, we can EMIT_EARLY here.
*/
r600_init_command_buffer(cb, 256);
@@ -818,7 +818,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
* R_008E28_SQ_STATIC_THREAD_MGMT3
*/
/* XXX: We may need to adjust the thread and stack resouce
/* XXX: We may need to adjust the thread and stack resource
* values for 3D/compute interop */
r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
src/gallium/drivers/r600/evergreen_state.c
+2 -2
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@@ -3670,9 +3670,9 @@ void evergreen_init_state_functions(struct r600_context *rctx)
unsigned id = 1;
unsigned i;
/* !!!
* To avoid GPU lockup registers must be emited in a specific order
* To avoid GPU lockup registers must be emitted in a specific order
* (no kidding ...). The order below is important and have been
* partialy infered from analyzing fglrx command stream.
* partially inferred from analyzing fglrx command stream.
*
* Don't reorder atom without carefully checking the effect (GPU lockup
* or piglit regression).
src/gallium/drivers/r600/r600_asm.h
+2 -2
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@@ -245,8 +245,8 @@ struct r600_bytecode {
unsigned ar_chan;
unsigned ar_handling;
unsigned r6xx_nop_after_rel_dst;
bool index_loaded[2];
unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */
bool index_loaded[2];
unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */
unsigned debug_id;
struct r600_isa* isa;
};