vc4: introduce VC4_DBG() macro to make VC4_DEBUG checks consistent
The main issue was the inconsistent use of `unlikely()`, but the macro also simplifies the code a little bit. Signed-off-by: Eric Engestrom <eric@igalia.com> Reviewed-by: Juan A. Suarez <jasuarez@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18086>
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e178ecf8a9
@@ -56,7 +56,7 @@ vc4_bo_label(struct vc4_screen *screen, struct vc4_bo *bo, const char *fmt, ...)
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* (for debugging a single app's allocation).
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*/
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#ifndef DEBUG
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if (!(vc4_debug & VC4_DEBUG_SURFACE))
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if (!VC4_DBG(SURFACE))
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return;
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#endif
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va_list va;
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@@ -550,7 +550,7 @@ vc4_wait_seqno(struct vc4_screen *screen, uint64_t seqno, uint64_t timeout_ns,
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if (screen->finished_seqno >= seqno)
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return true;
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if (unlikely(vc4_debug & VC4_DEBUG_PERF) && timeout_ns && reason) {
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if (VC4_DBG(PERF) && timeout_ns && reason) {
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if (vc4_wait_seqno_ioctl(screen->fd, seqno, 0) == -ETIME) {
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fprintf(stderr, "Blocking on seqno %lld for %s\n",
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(long long)seqno, reason);
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@@ -590,7 +590,7 @@ vc4_bo_wait(struct vc4_bo *bo, uint64_t timeout_ns, const char *reason)
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{
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struct vc4_screen *screen = bo->screen;
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if (unlikely(vc4_debug & VC4_DEBUG_PERF) && timeout_ns && reason) {
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if (VC4_DBG(PERF) && timeout_ns && reason) {
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if (vc4_wait_bo_ioctl(screen->fd, bo->handle, 0) == -ETIME) {
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fprintf(stderr, "Blocking on %s BO for %s\n",
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bo->name, reason);
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@@ -158,8 +158,8 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
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int err;
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/* Prevent dumping of the shaders built during context setup. */
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uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
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vc4_debug &= ~VC4_DEBUG_SHADERDB;
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uint32_t saved_shaderdb_flag = vc4_mesa_debug & VC4_DEBUG_SHADERDB;
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vc4_mesa_debug &= ~VC4_DEBUG_SHADERDB;
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vc4 = rzalloc(NULL, struct vc4_context);
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if (!vc4)
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@@ -202,7 +202,7 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
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if (!vc4->blitter)
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goto fail;
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vc4_debug |= saved_shaderdb_flag;
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vc4_mesa_debug |= saved_shaderdb_flag;
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vc4->sample_mask = (1 << VC4_MAX_SAMPLES) - 1;
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@@ -426,7 +426,7 @@ struct vc4_depth_stencil_alpha_state {
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};
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#define perf_debug(...) do { \
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if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
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if (VC4_DBG(PERF)) \
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fprintf(stderr, __VA_ARGS__); \
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if (unlikely(vc4->debug.debug_message)) \
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util_debug_message(&vc4->debug, PERF_INFO, __VA_ARGS__); \
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@@ -525,7 +525,7 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
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if (job->bo_space > 128 * 1024 * 1024)
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vc4_flush(pctx);
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if (vc4_debug & VC4_DEBUG_ALWAYS_FLUSH)
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if (VC4_DBG(ALWAYS_FLUSH))
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vc4_flush(pctx);
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}
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@@ -380,7 +380,7 @@ vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job)
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goto done;
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}
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if (vc4_debug & VC4_DEBUG_CL) {
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if (VC4_DBG(CL)) {
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fprintf(stderr, "BCL:\n");
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vc4_dump_cl(job->bcl.base, cl_offset(&job->bcl), false);
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}
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@@ -486,7 +486,7 @@ vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job)
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}
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}
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if (!(vc4_debug & VC4_DEBUG_NORAST)) {
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if (!VC4_DBG(NORAST)) {
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int ret;
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ret = vc4_ioctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
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@@ -511,7 +511,7 @@ vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job)
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}
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}
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if (vc4_debug & VC4_DEBUG_ALWAYS_SYNC) {
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if (VC4_DBG(ALWAYS_SYNC)) {
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if (!vc4_wait_seqno(vc4->screen, vc4->last_emit_seqno,
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PIPE_TIMEOUT_INFINITE, "sync")) {
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fprintf(stderr, "Wait failed.\n");
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@@ -2327,14 +2327,14 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
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NIR_PASS_V(c->s, nir_convert_from_ssa, true);
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if (vc4_debug & VC4_DEBUG_SHADERDB) {
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if (VC4_DBG(SHADERDB)) {
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fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id,
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count_nir_instrs(c->s));
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}
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if (vc4_debug & VC4_DEBUG_NIR) {
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if (VC4_DBG(NIR)) {
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fprintf(stderr, "%s prog %d/%d NIR:\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id);
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@@ -2368,7 +2368,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
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break;
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}
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if (vc4_debug & VC4_DEBUG_QIR) {
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if (VC4_DBG(QIR)) {
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fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id);
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@@ -2382,7 +2382,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
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qir_schedule_instructions(c);
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qir_emit_uniform_stream_resets(c);
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if (vc4_debug & VC4_DEBUG_QIR) {
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if (VC4_DBG(QIR)) {
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fprintf(stderr, "%s prog %d/%d QIR:\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id);
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@@ -2393,7 +2393,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
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qir_reorder_uniforms(c);
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vc4_generate_code(vc4, c);
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if (vc4_debug & VC4_DEBUG_SHADERDB) {
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if (VC4_DBG(SHADERDB)) {
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fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id,
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@@ -2430,7 +2430,7 @@ vc4_shader_state_create(struct pipe_context *pctx,
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} else {
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assert(cso->type == PIPE_SHADER_IR_TGSI);
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if (vc4_debug & VC4_DEBUG_TGSI) {
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if (VC4_DBG(TGSI)) {
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fprintf(stderr, "prog %d TGSI:\n",
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so->program_id);
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tgsi_dump(cso->tokens, 0);
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@@ -2461,7 +2461,7 @@ vc4_shader_state_create(struct pipe_context *pctx,
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so->base.type = PIPE_SHADER_IR_NIR;
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so->base.ir.nir = s;
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if (vc4_debug & VC4_DEBUG_NIR) {
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if (VC4_DBG(NIR)) {
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fprintf(stderr, "%s prog %d NIR:\n",
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gl_shader_stage_name(s->info.stage),
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so->program_id);
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@@ -2621,7 +2621,7 @@ vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
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shader->fs_threaded = c->fs_threaded;
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if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
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if (VC4_DBG(SHADERDB) && stage == QSTAGE_FRAG) {
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fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id,
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@@ -314,7 +314,7 @@ qir_calculate_live_intervals(struct vc4_compile *c)
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qir_compute_start_end(c, c->num_temps);
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if (vc4_debug & VC4_DEBUG_SHADERDB) {
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if (VC4_DBG(SHADERDB)) {
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int last_ip = 0;
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for (int i = 0; i < c->num_temps; i++)
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last_ip = MAX2(last_ip, c->temp_end[i]);
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@@ -679,14 +679,14 @@ vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
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cycles += c->qpu_inst_count - inst_count_at_schedule_time;
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if (vc4_debug & VC4_DEBUG_SHADERDB) {
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if (VC4_DBG(SHADERDB)) {
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fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d estimated cycles\n",
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qir_get_stage_name(c->stage),
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c->program_id, c->variant_id,
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cycles);
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}
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if (vc4_debug & VC4_DEBUG_QPU)
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if (VC4_DBG(QPU))
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vc4_dump_program(c);
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vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
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@@ -45,7 +45,7 @@ vc4_resource_bo_alloc(struct vc4_resource *rsc)
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struct pipe_screen *pscreen = prsc->screen;
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struct vc4_bo *bo;
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if (vc4_debug & VC4_DEBUG_SURFACE) {
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if (VC4_DBG(SURFACE)) {
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fprintf(stderr, "alloc %p: size %d + offset %d -> %d\n",
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rsc,
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rsc->slices[0].size,
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@@ -410,7 +410,7 @@ vc4_setup_slices(struct vc4_resource *rsc, const char *caller)
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offset += slice->size;
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if (vc4_debug & VC4_DEBUG_SURFACE) {
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if (VC4_DBG(SURFACE)) {
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static const char tiling_chars[] = {
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[VC4_TILING_FORMAT_LINEAR] = 'R',
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[VC4_TILING_FORMAT_LT] = 'L',
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@@ -73,7 +73,7 @@ static const struct debug_named_value vc4_debug_options[] = {
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", vc4_debug_options, 0)
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uint32_t vc4_debug;
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uint32_t vc4_mesa_debug;
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static const char *
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vc4_screen_get_name(struct pipe_screen *pscreen)
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@@ -588,7 +588,7 @@ vc4_screen_create(int fd, struct renderonly *ro)
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vc4_fence_screen_init(screen);
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vc4_debug = debug_get_option_vc4_debug();
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vc4_mesa_debug = debug_get_option_vc4_debug();
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#ifdef USE_VC4_SIMULATOR
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vc4_simulator_init(screen);
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@@ -37,6 +37,10 @@
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struct vc4_bo;
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extern uint32_t vc4_mesa_debug;
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#define VC4_DBG(flag) unlikely(vc4_mesa_debug & VC4_DEBUG_ ## flag)
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#define VC4_DEBUG_CL 0x0001
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#define VC4_DEBUG_QPU 0x0002
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#define VC4_DEBUG_QIR 0x0004
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@@ -117,8 +121,6 @@ vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
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enum pipe_shader_ir ir,
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enum pipe_shader_type shader);
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extern uint32_t vc4_debug;
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void
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vc4_fence_screen_init(struct vc4_screen *screen);
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@@ -377,7 +377,7 @@ vc4_dump_to_file(struct vc4_exec_info *exec)
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struct drm_vc4_get_hang_state_bo *bo_state;
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unsigned int dump_version = 0;
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if (!(vc4_debug & VC4_DEBUG_DUMP))
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if (!VC4_DBG(DUMP))
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return;
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state = calloc(1, sizeof(*state));
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@@ -477,7 +477,7 @@ vc4_simulator_submit_cl_ioctl(int fd, struct drm_vc4_submit_cl *args)
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if (ret)
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return ret;
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if (vc4_debug & VC4_DEBUG_CL) {
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if (VC4_DBG(CL)) {
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fprintf(stderr, "RCL:\n");
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vc4_dump_cl(sim_state.mem + exec.ct1ca,
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exec.ct1ea - exec.ct1ca, true);
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