vk/graphics_state: handle null pipeline state structs in creation
when these members are null, the corresponding graphics states should be initialized with sensible default values Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22236>
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dfc01aea83
@@ -279,6 +279,8 @@ vk_vertex_input_state_init(struct vk_vertex_input_state *vi,
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assert(!IS_DYNAMIC(VI));
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memset(vi, 0, sizeof(*vi));
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if (!vi_info)
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return;
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for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
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const VkVertexInputBindingDescription *desc =
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@@ -350,6 +352,10 @@ vk_input_assembly_state_init(struct vk_input_assembly_state *ia,
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const BITSET_WORD *dynamic,
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const VkPipelineInputAssemblyStateCreateInfo *ia_info)
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{
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memset(ia, 0, sizeof(*ia));
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if (!ia_info)
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return;
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/* From the Vulkan 1.3.224 spec:
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*
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* "VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY specifies that the topology
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@@ -377,14 +383,17 @@ vk_tessellation_state_init(struct vk_tessellation_state *ts,
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const BITSET_WORD *dynamic,
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const VkPipelineTessellationStateCreateInfo *ts_info)
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{
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if (IS_DYNAMIC(TS_PATCH_CONTROL_POINTS)) {
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ts->patch_control_points = 0;
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} else {
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*ts = (struct vk_tessellation_state) {
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.domain_origin = VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT,
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};
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if (!ts_info)
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return;
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if (!IS_DYNAMIC(TS_PATCH_CONTROL_POINTS)) {
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assert(ts_info->patchControlPoints <= UINT8_MAX);
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ts->patch_control_points = ts_info->patchControlPoints;
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}
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ts->domain_origin = VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
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if (!IS_DYNAMIC(TS_DOMAIN_ORIGIN)) {
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const VkPipelineTessellationDomainOriginStateCreateInfo *ts_do_info =
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vk_find_struct_const(ts_info->pNext,
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@@ -410,6 +419,8 @@ vk_viewport_state_init(struct vk_viewport_state *vp,
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const VkPipelineViewportStateCreateInfo *vp_info)
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{
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memset(vp, 0, sizeof(*vp));
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if (!vp_info)
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return;
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if (!IS_DYNAMIC(VP_VIEWPORT_COUNT)) {
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assert(vp_info->viewportCount <= MESA_VK_MAX_VIEWPORTS);
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@@ -501,7 +512,10 @@ vk_rasterization_state_init(struct vk_rasterization_state *rs,
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.rasterization_order_amd = VK_RASTERIZATION_ORDER_STRICT_AMD,
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.provoking_vertex = VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT,
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.line.mode = VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT,
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.depth_clip_enable = IS_DYNAMIC(RS_DEPTH_CLAMP_ENABLE) ? VK_MESA_DEPTH_CLIP_ENABLE_NOT_CLAMP : VK_MESA_DEPTH_CLIP_ENABLE_FALSE,
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};
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if (!rs_info)
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return;
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if (!IS_DYNAMIC(RS_RASTERIZER_DISCARD_ENABLE))
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rs->rasterizer_discard_enable = rs_info->rasterizerDiscardEnable;
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@@ -516,9 +530,7 @@ vk_rasterization_state_init(struct vk_rasterization_state *rs,
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* depth clipping is disabled when
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* VkPipelineRasterizationStateCreateInfo::depthClampEnable is VK_TRUE.
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*/
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if (IS_DYNAMIC(RS_DEPTH_CLAMP_ENABLE)) {
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rs->depth_clip_enable = VK_MESA_DEPTH_CLIP_ENABLE_NOT_CLAMP;
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} else {
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if (!IS_DYNAMIC(RS_DEPTH_CLAMP_ENABLE)) {
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rs->depth_clamp_enable = rs_info->depthClampEnable;
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rs->depth_clip_enable = rs_info->depthClampEnable ?
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VK_MESA_DEPTH_CLIP_ENABLE_FALSE :
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@@ -661,9 +673,11 @@ vk_multisample_state_init(struct vk_multisample_state *ms,
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const BITSET_WORD *dynamic,
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const VkPipelineMultisampleStateCreateInfo *ms_info)
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{
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if (IS_DYNAMIC(MS_RASTERIZATION_SAMPLES)) {
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ms->rasterization_samples = 0;
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} else {
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memset(ms, 0, sizeof(*ms));
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if (!ms_info)
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return;
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if (!IS_DYNAMIC(MS_RASTERIZATION_SAMPLES)) {
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assert(ms_info->rasterizationSamples <= MESA_VK_MAX_SAMPLES);
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ms->rasterization_samples = ms_info->rasterizationSamples;
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}
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@@ -758,7 +772,11 @@ vk_depth_stencil_state_init(struct vk_depth_stencil_state *ds,
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const BITSET_WORD *dynamic,
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const VkPipelineDepthStencilStateCreateInfo *ds_info)
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{
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memset(ds, 0, sizeof(*ds));
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*ds = (struct vk_depth_stencil_state) {
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.stencil.write_enable = true,
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};
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if (!ds_info)
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return;
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ds->depth.test_enable = ds_info->depthTestEnable;
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ds->depth.write_enable = ds_info->depthWriteEnable;
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@@ -766,9 +784,7 @@ vk_depth_stencil_state_init(struct vk_depth_stencil_state *ds,
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ds->depth.bounds_test.enable = ds_info->depthBoundsTestEnable;
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ds->depth.bounds_test.min = ds_info->minDepthBounds;
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ds->depth.bounds_test.max = ds_info->maxDepthBounds;
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ds->stencil.test_enable = ds_info->stencilTestEnable;
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ds->stencil.write_enable = true;
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vk_stencil_test_face_state_init(&ds->stencil.front, &ds_info->front);
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vk_stencil_test_face_state_init(&ds->stencil.back, &ds_info->back);
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}
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@@ -907,7 +923,11 @@ vk_color_blend_state_init(struct vk_color_blend_state *cb,
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const BITSET_WORD *dynamic,
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const VkPipelineColorBlendStateCreateInfo *cb_info)
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{
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memset(cb, 0, sizeof(*cb));
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*cb = (struct vk_color_blend_state) {
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.color_write_enables = BITFIELD_MASK(MESA_VK_MAX_COLOR_ATTACHMENTS),
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};
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if (!cb_info)
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return;
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cb->logic_op_enable = cb_info->logicOpEnable;
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cb->logic_op = cb_info->logicOp;
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@@ -937,11 +957,13 @@ vk_color_blend_state_init(struct vk_color_blend_state *cb,
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const VkPipelineColorWriteCreateInfoEXT *cw_info =
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vk_find_struct_const(cb_info->pNext, PIPELINE_COLOR_WRITE_CREATE_INFO_EXT);
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if (cw_info != NULL) {
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uint8_t color_write_enables = 0;
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assert(cb_info->attachmentCount == cw_info->attachmentCount);
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for (uint32_t a = 0; a < cw_info->attachmentCount; a++) {
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if (cw_info->pColorWriteEnables[a])
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cb->color_write_enables |= BITFIELD_BIT(a);
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color_write_enables |= BITFIELD_BIT(a);
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}
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cb->color_write_enables = color_write_enables;
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} else {
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cb->color_write_enables = BITFIELD_MASK(cb_info->attachmentCount);
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}
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@@ -1438,8 +1460,9 @@ vk_graphics_pipeline_state_fill(const struct vk_device *device,
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const VkPipelineSampleLocationsStateCreateInfoEXT *sl_info = NULL;
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struct vk_sample_locations_state *new_sl = NULL;
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if (needs & MESA_VK_GRAPHICS_STATE_MULTISAMPLE_BIT) {
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sl_info = vk_find_struct_const(info->pMultisampleState->pNext,
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PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
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if (info->pMultisampleState)
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sl_info = vk_find_struct_const(info->pMultisampleState->pNext,
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PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
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if (needs_sample_locations_state(dynamic, sl_info)) {
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if (all == NULL) {
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vk_multialloc_add(&ma, &new_sl, struct vk_sample_locations_state, 1);
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